Xilinx, Inc.

Jonathan Jung-Ching Ho

Hong-Tsz Pan

Yan E Wang

Kevin T Look

Nui Chong

Qi Lin

Yuhao Luo

Xin X Wu

Shih-Cheng Hsueh

Yuezhen Fan

Bang-Thu Nguyen

Hing Yee Angela Wong

An interconnect structure includes a substrate, a first diffusion region within the substrate, a plurality of first lines on the substrate and the first diffusion region, a first enclosure coupled to an end of the plurality of first lines, and a first contact within the first enclosure. The interconnect structure further includes a second diffusion region within the substrate, a plurality of second lines on the substrate and the second diffusion region, a second enclosure coupled to an end of the plurality of second lines, and a second contact within the second enclosure. A spacing can be present between the plurality of first lines and the plurality of second lines. The plurality of first lines, the first contact, the plurality of second lines, and the second contact are trimmed, but the first enclosure, the second enclosure, and the spacing are not trimmed.

Interconnect structure

A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.

Double exposure semiconductor process for improved process margin

Fluid-based dielectric material is used to backfill multiple patterned metal layers of an IC on a wafer. The patterned metal layers are fabricated using conventional CMOS techniques, and are IMD layers in particular embodiments. The dielectric material(s) are etched out of the IC to form a metal network, and fluid dielectric material precursor, such as a polyarylene ether-based resin, is applied to the wafer to backfill the metal network with low-k fluid-based dielectric material.

Method of fabricating CMOS devices using fluid-based dielectric materials

Method and apparatus for compensating an integrated circuit design for mechanical stress effects. One aspect of the invention relates to designing an integrated circuit. Layout data is obtained that describes layers of the integrated circuit. At least one of the layers is analyzed to detect at least one structure susceptible to damage from mechanical stress. A bias is automatically added to each of the at least one structure to reduce mechanical stress of the at least one structure as fabricated. Augmented layout data is then provided for the integrated circuit.

Method and apparatus for compensating an integrated circuit layout for mechanical stress effects

A reticle and pellicle that are modified to prevent ESD damage to the masking material between portions of the lithographic mask pattern on the reticle during an integrated circuit fabrication process. The modification involves providing conducting lines on the glass side of the reticle and on the surface of the pellicle to balance any buildup of electrostatic charges on those devices, thereby reducing or eliminating the induction of opposite charges onto adjacent mask pattern features on the reticle and preventing the melting and bridging of those mask pattern features and the defects caused by such melting or bridging. The conductive metal lines may have a smaller width than the smallest resolution value of the reduction lens used in the mask pattern transfer process, and may also be located outside of the focal plane of the reduction lens to avoid transfer of the images of the conductive lines onto the target semiconductor substrate during the mask pattern transfer process.

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Fremont, CA, United States of America

Jonathan Jung-Ching Ho