Micron Technology Incorporated

Jonathan J Strand

Jonathan D Harms

Sukneet Singh Basuta

Shashank Bangalore Lakshman

Durai Vishak Nirmal Ramaswamy

Adam D Johnson

Xiaonan Chen

Angelo Visconti

Kevin T Majerus

Riccardo Pazzocco

Methods, systems, and devices for robust functionality for memory management associated with high-temperature storage are described. A memory device may apply a pattern (e.g., an imprint conditioning or deletion pattern) to at least a portion of memory cells of a memory array associated with a memory device before or after a power state procedure. The memory device may determine the pattern from various possible patterns, where the pattern may indicate a data state for each memory cell of the portion of memory cells. The pattern may indicate a same data state for each memory cell, an alternating data state for each memory cell, or an asymmetric switching pattern over a plurality of cycles, or any combination thereof. The memory device may write a respective logic value to at least some of the one or more memory cells of the portion of memory cells according to the pattern.

Robust functionality for memory management associated with high-temperature storage and other conditions

Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

Imprint management for memory

Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

Imprint recovery for memory arrays

Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

Imprint recovery for memory cells

Imprint recovery management for memory systems

Methods, systems, and devices for charge leakage detection for memory system reliability are described. In accordance with examples as disclosed herein, a memory system may employ memory management techniques configured to identify precursors of charge leakage in a memory device, and take preventative action based on such identified precursors. For example, a memory system may be configured to perform a leakage detection evaluation for a memory array, which may include various biasing and evaluation operations to identify whether a leakage condition of the memory array may affect operational reliability. Based on such an evaluation, the memory device, or a host device in communication with the memory device, may take various preventative measures to avoid operational failures of the memory device or host device that may result from ongoing operation of a memory array associated with charge leakage, thereby improving reliability of the memory system.

Charge leakage detection for memory system reliability

Memory programming methods and memory systems are described. One example memory programming method includes first applying a first signal to a memory cell to attempt to program the memory cell to a desired state, wherein the first signal corresponds to the desired state, after the first applying, determining that the memory cell failed to place in the desired state, after the determining, second applying a second signal to the memory cell, wherein the second signal corresponds to another state which is different than the desired state, and after the second applying, third applying a third signal to the memory cell to program the memory cell to the desired state, wherein the third signal corresponds to the desired state. Additional method and apparatus are described.

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Boise, ID, United States of America

Jonathan J Strand