Agere Systems Inc.

Lucent Technologies Inc.

Agere Systems Guardian Corp.

Lsi Corporation

At&t Bell Laboratories

Jonathan Herman Fischer

Donald Raymond Laturell

Lane Allen Smith

Weilin Zhu

Keith Eugene Hollenbach

Michael G Williams

Michael S Toth

Wenzhe Luo

Steven Brooke Witmer

Joseph M Cannon

Vladimir Sindalovsky

Walter G Soto

Bernard Lee Morris

Roger A Fratti

Milton L Embree

Bahram Ghaffarzadeh Kermani

Zhigang Ma

John Peter Veschi

Michael Straub

Paul David Hendricks

James Patrick Howley

Mingdeng Chen

Kouros Azimi

John T Rehberg

Robert Frederick Lee

James M Little

Interface circuitry of a storage device or other type of processing device comprises a digital input detector and an adaptive power supply. The digital input detector comprises an input transistor. The adaptive power supply provides a variable supply voltage to the digital input detector that varies with a threshold voltage of the input transistor. In one embodiment, the variable supply voltage provided to the digital input detector by the adaptive power supply varies with the threshold voltage of the input transistor about a set point value determined as a function of an expected logic level of an input signal. For example, the set point value may be determined as a function of a minimum expected logic high input signal level. In such an arrangement, the input transistor is biased at or close to the threshold voltage for an input signal having the minimum expected logic high input signal level.

Digital input detector and associated adaptive power supply

A MOS-type semiconductor input capacitor protection circuit and system is described. In one embodiment, the system includes a MOS device configured as an input capacitor and configured to receive an input bias voltage. A bias monitor circuit is configured to monitor the input bias voltage and apply a selective capacitor bias voltage to the input capacitor so as to limit the voltage across the input capacitor to a level below a threshold voltage.

Input capacitor protection circuit

In one embodiment, a low cost, simple circuit for detecting an off-hook condition of a telecommunication line comprising tip and ring signal lines is provided. The circuit comprises a voltage divider for coupling between the tip and ring lines without an intervening transistor and having a node at which is presented a scaled version of a voltage across the voltage divider. The circuit further comprises a transistor having a control terminal coupled to the node, a first current flow terminal coupled to a voltage source, and a second current flow terminal coupled to an output terminal, wherein the output terminal bears a value that is indicative of a voltage across the tip and ring lines and thus whether the telecommunication line is off-hook.

Method and apparatus for non-disruptive telecommunication loop condition determination

A MOS-type semiconductor clamping circuit is disclosed. The clamping circuit comprises a pmos device coupled to a nmos device in series to form the clamping circuit to selectively clamp a signal to a reference voltage, the signal configured to swing between a first voltage and a second voltage about the reference voltage. When the signal is swung between the first voltage and the second voltage, the pmos device and the nmos device are subjected to a voltage swing less than the voltage swing between the first voltage and the second voltage.

Clamp circuit using PMOS and NMOS devices

A sample and hold circuit is disclosed that provides longer hold times. An analog multiplexer circuit is also disclosed that exhibits low switch leakage. The analog multiplexer circuit comprises a shared node, a plurality of input circuits, a control input for selecting one or more of the plurality of input circuits, and an amplifier coupled to the shared node. Each input circuit comprises an input node, a primary input switch for selectively coupling an input to the input node, and a secondary input switch for selectively coupling the input node to the shared node, wherein the secondary input switch comprises one or more transistor switches. The parasitic drain and source diodes of one or more transistor switches in secondary input switch in a selected input circuit are coupled to a voltage that is distinct from an input signal of the selected input circuit. For input circuits not selected, the parasitic drain and source diodes of secondary input switch transistor switches are coupled to an output of the amplifier.

Analog multiplexer circuits and methods

The invention provides a low cost, simple, circuit for detecting the condition of a telephone line.

A sample and hold circuit is disclosed that provides longer hold times. The sample and hold circuit can be used in a disc drive to provide improved read-to-write and write-to-read mode transitions. The sample and hold circuit has an input and an output, and includes at least one capacitive element for retaining a charge. The capacitive element is connected to a node between the input and the output. The sample and hold circuit includes at least one input switch to selectively connect the capacitive element to the input and at least one output switch to selectively connect the capacitive element to the output. In addition, an amplifier is connected to the node and has an offset voltage. In this manner, a voltage drop across at least one of the input and output switches is limited to the offset voltage.

Long hold time sample and hold circuits

A current mirror circuit providing a fast turn on time. A node within the circuit is held at a first voltage when the current mirror is off to permit the node voltage to quickly reach a necessary value when the current mirror circuit is turned on.

Current mirrors having fast turn-on time

A write head for a magnetic storage system energizes a write coil for a plurality of bit intervals and selectively shutters the magnetic field to alter a magnetic domain of a magnetic storage medium for each bit interval. The position of the shutter may be controlled using a micro-electro mechanical system. Magnetic pole segments provide a loop between the write coil and the magnetic storage medium. Magnetic shielding on the shutter mechanisms controls the reflection of the magnetic fields. In a rewritable magnetic storage system, a first write coil generates a positive magnetic field and a second write coil generates a negative magnetic field. A shutter is associated with each write coil to selectively allow the positive or negative magnetic fields to alter the magnetic domain of the magnetic storage medium. The positive or negative magnetic fields can alter the magnetic domain in a collocated region of the magnetic storage medium to avoid jitter.

Magnetic storage write heads using micro-electro mechanical shutters

A bi-directional single-conductor interface is provided, comprising (1) a switching means for applying a voltage level to the interface that is outside a normal voltage operating range for the interface and for removing the applied voltage level at an end of a specified time duration; and (2) a timer initiated by detection of the applied voltage and arranged to include a timing interval following removal of the applied voltage. With the interface of the invention, data is caused to be transmitted via the interface in a first direction during the timing interval of the timer, and in an opposite direction during other times.

Bi-directional interface for low data rate application

An apparatus for supplying a load current. The apparatus comprises a first differential amplifier producing a differential output signal and an output buffer comprising a first and a second parallel emitter follower transistors each producing a current responsive to the differential output signal. A second differential amplifier responsive to the differential output signal controls current mirror masters that in turn control current source mirrors. Current supplied by each of the current sources mirrors in cooperation with the current produced by each of the first and second transistors produce the load current.

Composite output stage for hard disk drive preamplifier

The present invention provides a method and apparatus, such as an integrated circuit, to control the optical midpoint power level and the extinction ratio of a semiconductor laser and maintain the optical midpoint power level and the extinction ratio substantially constant at corresponding predetermined levels. Apparatus embodiments include a semiconductor laser, a modulator, a photodetector, an optical midpoint controller, and an extinction ratio controller. The semiconductor laser is capable of transmitting an optical signal in response to a modulation current. The modulator is capable of providing the modulation current to the semiconductor laser, with the modulation current corresponding to an input data signal. The photodetector, which is optically coupled to the semiconductor laser, is capable of converting the optical signal into a photodetector current. In response to the photodetector current, the optical midpoint controller is capable of adjusting the forward bias current of the semiconductor laser, and the extinction ratio controller is capable of adjusting the modulation current provided by the modulator to the semiconductor laser, to respectively generate the optical signal having substantially a predetermined optical midpoint power level and a predetermined extinction ratio.

Optical midpoint power control and extinction ratio control of a semiconductor laser

A circuit is described which uses a thick gate oxide device in the input stage and a thin gate oxide device in a second stage that is connected to the input stage. The input stage thick gate oxide device provides a low input gate leakage current. The thin gate oxide device in the second stage has high performance characteristics due to the use of the thin gate oxide device. The circuit thereby has high performance characteristics and low input gate leakage current. In various applications, the circuit may be, for example, an amplifier, a differential amplifier, a variable gain differential amplifier, or an operational amplifier in a sample and hold circuit. A guideline is provided where the thick gate oxide layer is about 1.5&#xd7; the thickness of the thin gate oxide layer. Also, a design to control the circuit's common mode voltage using common mode voltage feedback is described.

High performance differential amplifiers with thick oxide devices for high impedance nodes

The present invention relates to an application layer function outside the BLUETOOTH protocol which associates a BLUETOOTH unique address, i.e., the 48-bit unique BD_ADDR address, with a short passcode or PIN which is associated with a particular type of BLUETOOTH device in a particular piconet. The passcode or PIN can be pre-determined by the manufacturer of the BLUETOOTH device, or can be input and defined by the user. Upon installation in a piconet, in one embodiment shown and described with reference to, a user can be asked to manually input a particular passcode or PIN into a relevant piconet device, and an inquiry can be broadcast to all communicating piconet devices and only those other piconet devices having a matching passcode or PIN associated therewith can automatically forward their respective 48-bit unique BD_ADDR addresses to the inquiring piconet device. Alternatively, a user can inquire and be provided with a list of available passcodes or PINs already established by other devices in the piconet, and select a particular passcode or PIN associated with one or more other piconet devices. The passcode or personal identification number (PIN) may be input upon electronic device setup (e.g., a four character code). The passcode or PIN may be numeric, text, or alphanumeric.

Growing community of inventors

Longmont, CO, United States of America

Jonathan Herman Fischer