Qorvo Us, Inc.

Rf Micro Devices, Inc.

Freescale Semiconductor,inc.

Globalfoundries Inc.

Jonathan Hale Hammond

Julio C Costa

Jan Edward Vandemeer

Jon Chadwick

Merrill Albert Hatcher, Jr

Nadim Khlat

Tony Ivanov

David Jandzinski

Anthony K Stamper

Marcus Granger-Jones

Thomas L McDevitt

Bishnu Prasanna Gogoi

Ruediger Bauder

Thomas Scott Morris

Michael Carroll

Daniel N Koury, Jr

Philippe Gorisse

Felix Patrick Anderson

Gary G Li

Stephen Craig Parker

Walter Anthony Wohlmuth

Stephen Parker

Jr Merrill Albert Hatcher

The present disclosure relates to a wafer-level fan-out package that includes a first thinned die, a second die, a multilayer redistribution structure underneath the first thinned die and the second die, a first mold compound over the second die, a second mold compound over the multilayer redistribution structure, and around the first thinned die and the second die, and a third mold compound. The second mold compound extends beyond the first thinned die to define an opening within the second mold compound and over the first thinned die, such that a top surface of the first thinned die is at a bottom of the opening. A top surface of the first mold compound and a top surface of the second mold compound are coplanar. The third mold compound fills the opening and is in contact with the top surface of the first thinned die.

Wafer-level fan-out package with enhanced performance

The present disclosure relates to a packaging process to enhance performance of a wafer-level package. The disclosed package includes multiple mold compounds, a multilayer redistribution structure, and a thinned die with a device layer and die bumps underneath the device layer. The multilayer redistribution structure includes package contacts at a bottom of the multilayer redistribution structure and redistribution interconnects connecting the die bumps to the package contacts. A first mold compound resides around the thinned die to encapsulate sidewalls of the thinned die, and extends beyond a top surface of the thinned die to define an opening over the thinned die. A second mold compound resides between the multilayer redistribution structure and the first mold compound to encapsulate a bottom surface of the device layer and each die bump. A third mold compound fills the opening and is in contact with the top surface of the thinned die.

The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.

Wafer-level package with enhanced performance and manufacturing method thereof

The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.

Wafer-level package with enhanced performance

Microelectromechanical system (MEMS) switches that provide low contact resistance over a large number of open and close contact cycles are disclosed. A MEMS switch device may include a plurality of parallel MEMS switches with a first MEMS switch that is configured differently in such a manner to close first and/or open last during open and close cycles. In this regard, the first MEMS switch may experience increased contact resistance over a large number of open and close cycles while other MEMS switches maintain a low contact resistance. In certain embodiments, the first MEMS switch is controlled by a different control signal to open and close differently than the other MEMS switches. In certain embodiments, a common control signal controls a plurality of MEMS switches and the first MEMS switch is mechanically different such that it opens and closes differently than other MEMS switches.

Switch arrangements for microelectromechanical systems

A method for processing product wafers using carrier substrates is disclosed. The method includes a step of bonding a first carrier wafer to a first product wafer using a first temporary adhesion layer between a first carrier wafer surface and a first product wafer first surface. Another step includes bonding a second carrier wafer to a second product wafer using a second temporary adhesion layer between a second carrier wafer surface and a second product wafer surface. Another step includes bonding the first product wafer to the second product wafer using a permanent bond between a first product wafer second surface and a second product wafer first surface. In exemplary embodiments, at least one processing step is performed on the first product wafer after the first temporary carrier wafer is bonded to the first product wafer before the second product wafer is permanently bonded to the first product wafer.

Method for processing product wafers using carrier substrates

The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die resides over a top surface of the multilayer redistribution structure. The multilayer redistribution structure includes at least one support pad that is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.

The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die includes a first device layer formed from glass materials. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.

The disclosure is directed to optimized switching circuitry utilizing MEMS (Microelectromechanical Systems) circuitry in series with solid state circuitry. Specifically, the MEMS circuitry includes a first MEMS circuit in parallel with (and separate from) a second MEMS circuit. A paired signal is defined as a transmit signal and a receive signal (in a single band) that are transmitted or received on separate paths or on separate nodes. The transmit signal is associated with the first MEMS circuit, and the receive signal is associated with the second MEMS circuit. The solid state circuitry switches between the first MEMS circuit and second MEMS circuit without requiring any switching in the first or second MEMS circuits.

Contact MEMS architecture for improved cycle count and hot-switching and ESD

This disclosure relates generally to radio frequency (RF) front-end circuitry for routing RF signals to and/or from one or more antennas. Exemplary RF front-end circuitry includes a multiple throw solid-state transistor switch (MTSTS) and a multiple throw microelectromechanical switch (MTMEMS). The MTSTS may be configured to selectively couple a first pole port to any one of a first set of throw ports. The MTMEMS is configured to selectively couple a second pole port to any one of a second set of throw ports. The second pole port of the MTMEMS is coupled to a first throw port in the first set of throw ports of the MTSTS. The MTSTS helps prevent hot switching in the MTMEMS since the first throw port of the MTSTS may be decoupled from the second pole port of the MTMEMS before decoupling the second pole port from a selectively coupled throw port of the MTMEMS.

RF front-end circuitry with transistor and microelectromechanical multiple throw switches

A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound residing on the top surface. A first mold compound is disposed on the top surface of the carrier. A first thinned flip chip die resides over a first portion of the first mold compound with interconnects extending through the first portion to the top surface wherein the first portion of the mold compound fills a region between the first flip chip die and the top surface. A second mold compound resides over the substrate and provides a first recess over the first flip chip die wherein the first recess extends to a first die surface of the first flip chip die. A third mold compound resides in the first recess and covers an exposed surface of the flip chip die.

Flip chip module with enhanced properties

Encapsulated MEMS switches are disclosed along with methods of manufacturing the same. A non-polymer based sacrificial layer is used to form the actuation member of the MEMS switch while a polymer based sacrificial layer is used to form the enclosure that encapsulates the MEMS switch. The first non-polymer based sacrificial layer allows for highly reliable MEMS switches to be manufactured while also protecting the MEMS switch from carbon contamination. The polymer based sacrificial layer allows for the manufacture of more spatially efficient encapsulated MEMS switches.

Encapsulated micro-electromechanical system switch and method of manufacturing the same

Encapsulated MEMS switches are disclosed along with methods of manufacturing the same. A first sacrificial layer is used to form the actuation member of the MEMS switch. A second sacrificial layer is used to form the enclosure that encapsulates the MEMS switch.

Growing community of inventors

Oak Ridge, NC, United States of America

Jonathan Hale Hammond