Texas Instruments Corporation

Jonathan H Shiell

Donald Edward Steiss

Steven D Krueger

Ian Chen

James O Bondi

George Z Cai

Patrick W Bosshart

Timothy David Anderson

Tod David Wolf

Ashwini K Nanda

Robert D Marshall, Jr

James E Brooks

Robert R Collins

Wilbur Christian Vogley

Joel J Graber

Robert John Cyran

David Harold Bartley

Robert W Milhaupt

Paul Knueven

Simonjit Dutta

Tai-Yuen Chan

George Z N Cai

George ZN Cai

A computer system ( ) comprising a central processing unit ( ) and a memory hierarchy. The memory hierarchy comprises a first cache memory ( ) and a second cache memory ( ). The first cache memory is operable to store non-pixel-information, wherein the non-pixel information is accessible for processing by the central processing unit. The second cache memory is higher in the memory hierarchy than the first cache memory, and has a number of storage locations operable to store non-pixel information ( ) and pixel data ( ). Lastly, the computer system comprises cache control circuitry ( ) for dynamically apportioning the number of storage locations such that a first group of the storage locations are for storing non-pixel information and such that a second group of the storage locations are for storing pixel data.

Microprocessor circuits, systems, and methods with combined on-chip pixel and non-pixel cache structure

This invention is memory system including plural memory banks logically disposed into an array of X rows and Y columns. A first decoder selectively powers one of the Y columns corresponding to a first predetermined set of address bits. A second decoder selectively powers one of the X rows corresponding to a second predetermined set of address bits. Multiplexers select the powered memory bank for data access. Thus one of the plural memory banks is powered and selected for memory access corresponding to the first and second predetermined sets of bits of the received address. This memory system is preferably a cache memory including a further column of memory banks for cache addresses and cache control data including at least a cache valid tag. A multiplexer selects one row corresponding to the second predetermined set of address bits. A valid and equal unit indicates whether data received from the third multiplexer includes a cache valid tag indicating a valid address and a cache address matching the received address. This indicates a cache hit.

Selectively powering X Y organized memory banks

The present invention is a code preparation system ( ) which accepts input code ( ) in intermediate code format, our source code format which is first translated into intermediate format, analyzes the intermediate code, then provides optimization information, hints, and/or directions (collectively referred to as &ldquo;optimization information&rdquo;) for optimizing execution of the intermediate code by a code interpretive runtime environment, such as a Java Virtual Machine. The code interpretive runtime environment is operable to selectively implement the optimization information received from the code preparation system ( ). The optimization information is provided to the code interpretive runtime environment in the form of additional attributes added to a class file ( ) generated by the code preparation system ( ). Processing in accordance with the received optimization information allows the code interpretive runtime environment to execute code more efficiently and to manage use of its resources more effectively, particularly when executing in a limited resource computing environment. Such limited resource computing environments include set-top boxes, digital personal assistants, etc.

Method and system of providing dynamic optimization information in a code interpretive runtime environment

A data processing circuit has an adder unit divided into plural sections. Each section receives a subset of the bits of the operands and generates a subset of the bits of the resultant. A carry multiplexer is disposed between the sections. This carry multiplexer selects one of a plurality of possible carry inputs to the following sections. The data processing circuit may make the specification of the selection of the carry control multiplexers by: the opcode of the instruction; a combination of the opcode and an opcode modification field; an immediate field directly specifying carry control signals; or designation a carry control register which stores the carry control signals. The adder unit may be divided into sections of equal size or of unequal size.

Instruction set architecture with versatile adder carry control

In a computer system ( ) embodiment, there is included a memory ( ) and circuitry ( ) for prefetching information from the memory in response to a prefetch request. The system further includes a system resource ( ), wherein the system resource is burdened in response to a prefetch operation by the circuitry for prefetching information. The system resource is also further burdened in response to other circuitry ( ) using the system resource. The system further includes circuitry ( ) for determining a measure of the burden on the system resource. Lastly, the system includes circuitry ( ) for prohibiting prefetching of the information by the circuitry for prefetching information responsive to a comparison of the measure of the burden with a threshold. Other circuits, systems, and methods are also disclosed and claimed.

Microprocessor circuits, systems, and methods for conditioning information prefetching based on resource burden

A multiple cycle memory access unit issues a memory access load or store, delaying a predetermined number of instruction cycles between it activation and its initial data transfer. The multiple cycle memory access unit controls a predetermined plural number of accesses and operates independently and in parallel with the instruction flow of the data processor. The multiple cycle memory access unit delays a predetermined number of instruction cycles between sequential data transfers of the predetermined number of data transfers. This predetermined period may be the same as the initial delay or it may be determined independent of the initial delay. The operation of the multiple cycle memory access unit is subject to predication on an instruction specified data registers. The multiple cycle memory access unit preferably provides predetermined register number cycling among the plural data registers. The multiple cycle memory access unit preferably aborts operation, stops and saves its internal state on a predetermined event.

Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer

This invention is a very long instruction word data processor including plural data registers, plural functional units and plural program counters and is selectively operable in either a first or second mode. In the first mode, the data processor executes a single instruction stream. In the second mode, the data processor executes two independent program instruction streams simultaneously. In the second mode the data processor may respond to two instruction streams accessing only corresponding halves of the data registers and function units. Alternatively, the data processor may respond to a first instruction stream including instructions referencing the whole data processor employing A side function units by alternatively dispatching (1) instructions referencing the A side data registers and the A side function units and (2) instructions referencing the B side data registers and the B side function units. In the first mode, the data processor fetches N bits of instructions each cycle. In the second mode the data processor may fetch N bits of instructions for alternate program counters on alternate cycles or fetches N/2 bits of each of the first and second program counters. The data processor includes interrupt steering and masking control logic allowing instructions to control whether the first instruction stream or the second instruction stream receives interrupts.

Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism

A microprocessor (,) comprising a memory system (,) for outputting data in response to an address, wherein the memory system is further operable to receive a prefetch request having a predicted target data address. The microprocessor further includes a load target circuit (,or,), which comprises a first plurality of entries (,) of a first length and a second plurality of entries (,) of a second length. Each of the first plurality of entries comprises a value (ADDRESS TAG) for corresponding the entry to a corresponding first plurality of data fetching instructions. Further, each of the first plurality of entries further comprises a value (POINTER A) for indicating a corresponding predicted target data address. Each of the second plurality of entries also comprises a value (ADDRESS TAG) for corresponding each of the second plurality of entries to a corresponding second plurality of data fetching instructions. However, each of the second plurality of data fetching instructions is of a type for which it is undesirable to issue a prefetch request.

Microprocessor circuits, systems, and methods implementing a load target buffer with entries relating to prefetch desirability

In one embodiment, there is a single integrated circuit microprocessor (,). The microprocessor has an instruction pipeline (,) which comprises an execution stage (,) operable to process an information unit of a first length. The microprocessor further includes a cache circuit (,) comprising a memory (,) operable to store a transfer unit of information of a second length and accessible by the instruction pipeline. The second length corresponding to the capability of the cache circuit is greater than the first length corresponding to the execution stage operability. Lastly, the microprocessor includes a block move circuit (,) coupled to the cache circuit and operable to read/write a transfer unit of information of the first length into the memory of the cache circuit.

Microprocessor system with block move circuit disposed between cache circuits

A programmable logic device, such as a digital signal processor (DSP) (,), having a Chien search unit (,) is disclosed. The Chien search unit (,) is arranged to perform finite field arithmetic functions useful in identifying roots of a polynomial, as is useful in Reed-Solomon decoding, particularly, after the execution of a Euclidean array function. Galois field multipliers (,) perform finite field multiplication of coefficient values (&Lgr;) and powers of symbol values (&agr;); the products of such multiplications are written into the coefficient register (,) for use in connection with the next symbol value. Finite field adders (,) produce a final sum that is interrogated by zero detection circuitry (,) to determine whether a root is presented by the current symbol value. The provision of a Chien search execution unit (,) provides important efficiency so as to enable programmable logic devices, such as digital signal processors (,) and microprocessors to effect Reed-Solomon decoding.

Efficient hardware implementation of chien search polynomial reduction in reed-solomon decoding

A microprocessor (,) comprising a cache circuit (,) and circuitry (,) for issuing a prefetch request. The prefetch request (,) comprises an address (,) and requests information of a first size (,) from the cache circuit. The microprocessor also includes prefetch control circuitry (,), which comprises circuitry for receiving the prefetch request and evaluation circuitry for evaluating system parameters corresponding to the prefetch request. Additionally, the prefetch control circuitry comprises circuitry, responsive to the evaluation circuitry, for determining a size of information for a prefetch operation starting at the address from the cache circuit, where the prefetch operation corresponds to the prefetch request.

Prefetch circuity for prefetching variable size data

A microprocessor (,) for coupling to an external read/write memory (,) having an addressable storage space. This storage space stores cacheable digital data and non-cacheable (,) digital data. The microprocessor includes a data storage circuit (,) for storing a portion of the non-cacheable data. The microprocessor further includes an address storage circuit (,) for storing an address corresponding to the portion of the non-cacheable data. Still further, the microprocessor includes a counter (,) for advancing a count from an initial value (,) toward a threshold value (,) in response to an activity over time. The counter initiates its advancing operation in response to the data storage circuit receiving the portion of the non-cacheable data. Lastly, the microprocessor includes an indicator (,) for indicating the portion of the non-cacheable data in the data storage circuit is expired in response to the count reaching a threshold.

Microprocessor circuits and systems with life spanned storage circuit for storing non-cacheable data

A microprocessor (,) for coupling to an external read/write memory (,) having an addressable storage space for storing data. The microprocessor includes a data storage circuit (,) for storing a portion of the data, where that portion of data comprises non-cacheable data. The microprocessor further includes a class storage circuit (,) for storing a class identifier corresponding to the portion of the non-cacheable data, as well as an input (TERMINATE) for receiving a terminate signal and an input (CLASS) for receiving a class signal. Lastly, the microprocessor includes an indicator (,) for indicating that the portion of the non-cacheable data in the data storage circuit is expired in response to assertions of the terminate signal and the class signal matching the class identifier.

Class categorized storage circuit for storing non-cacheable data until receipt of a corresponding terminate signal

In a computer system (,) embodiment, there is included a memory (,) and circuitry (,) for prefetching information from the memory in response to a prefetch request. The system further includes a system resource (,), wherein the system resource is burdened in response to a prefetch operation by the circuitry for prefetching information. The system resource is also further burdened in response to other circuitry (,) using the system resource. The system further includes circuitry (,) for determining a measure of the burden on the system resource. Lastly, the system includes circuitry (,) for prohibiting prefetching of the information by the circuitry for prefetching information responsive to a comparison of the measure of the burden with a threshold. Other circuits, systems, and methods are also disclosed and claimed.

Microprocessor circuits, systems and methods for conditioning information prefetching based on resource burden

A microprocessor with an execution stage (,) including a plurality of execution units and an instruction memory (,) for storing instructions. The microprocessor further includes circuitry for retrieving (,) instructions from the instruction memory. This retrieving circuitry may retrieve one instruction simultaneously with the execution of another instruction by one of the plurality of execution units. Further, this retrieving circuitry includes a branch target memory (,) for storing a plurality of information fields (,) corresponding to a branch instruction. The information fields include at least a target instruction address (T,), a prediction field (P,) indicating whether or not program flow should pass to the target instruction address, and an accuracy measure (PPA,) indicating accuracy for past prediction fields. In operation, the circuitry for retrieving instructions retrieves (,), as a next instruction to follow the branch instruction, an instruction corresponding to the target instruction address in response to a function (TP,) responsive to the accuracy measure exceeding a predetermined threshold and the prediction field indicating program flow should pass to the target instruction address. Additionally, the circuitry for retrieving instructions retrieves (,), in response to the function responsive to the accuracy measure not exceeding a predetermined threshold, a first group of instructions, wherein the first group of instructions is sequentially arranged after the branching branch instruction and includes an instruction corresponding to the target instruction address.

Growing community of inventors

Plano, TX, United States of America

Jonathan H Shiell