Broadcom Corporation

Mediatek Corporation

Avago Technologies General IP Pte, Ltd.

Jonathan Fuchuen Lee

Chuen-Shen Bernard Shung

Andrew Hwang

John K Lenell

David Wang

Xiaogang Zhu

Gregory Youngblood

Kelly Yu

Takashi Tomita

Jack Qiu

Tom Hsiou-Cheng Kao

David (Wei) Wang

Zhaoqian Chen

Xiagang Zhu

A processing device includes a first memory interface for accessing a first memory device of a main memory. Each first memory interface is compatible with Low-Power Double-Data-Rate (LPDDR) signaling. The processing device further includes a second memory interface, which has different signaling characteristics from the first memory interface, for accessing a second memory device of the main memory. The second memory device has an access latency higher than the first memory device and lower than a secondary storage device. The first memory device and the second memory device may be used as a dual memory or a two-tiered memory.

Processor memory architecture

A method for processing packets includes performing by a plurality of processors integrated in a single NIC chip, the plurality of processors including at least a hardware processor and a firmware processor, receiving information identifying at least one packet to be processed. The method may include determining whether the identified packet is a large send offload packet. If the identified packet is a large send offload packet, the method may include selecting between at least the hardware processor and the firmware processor to process the large send offload packet. If the identified packet is not a large send offload packet, the method may include bypassing the hardware process and the firmware process, and read DMA processing the identified packet from a host memory.

Method and system for transmission control packet (TCP) segmentation offload

Drivers which control hardware devices in a network adapter chip are disabled prior to reducing power to a first portion of circuits in the network adapter chip. Power is received by a second portion of circuits which are utilized for detecting network activity and communicating the activity to processors. Upon network activity detection, the first portion of circuits receives power. Drivers are enabled subsequent to detection. Drivers are enabled after receiving power by the first portion of circuits. Processors control hardware devices, disable devices before power reduction, enable devices after network activity detection and enable devices after receiving power. The network adapter chip is reset for power reception. A power reduction mode is selected where drivers are disabled after reducing power. Drivers are enabled after hardware devices are enabled. A first state is characterized by no signal before disabling drivers. A second state is characterized by signal detection before receiving power.

Operating mode for extreme power savings when no network presence is detected

The present invention relates to a system and method adapted to optimize power consumption in a communication system used in a Gigabit Ethernet environment. The method comprises determining at least one power mode of a host from a plurality of possible host power modes. The method further comprises selecting at least one network interface power management state from a plurality of possible network interface power management states based, at least in part, on the determined power mode.

Method and system for optimizing power consumption in a mobile environment

Certain embodiments of a cable sense mode for intelligent power saving in the absence of a link pulse may include detecting an energy level of an Ethernet link. The Ethernet link may couple a network adapter chip to a network. The power supplied to the network adapter chip may be adjusted based on the detected energy level. Power may be supplied to the network adapter chip if the detected energy level of the Ethernet link is greater than or equal to a particular energy level. Power may be reduced to the network adapter chip if the detected energy level of the Ethernet link is less than a particular energy level. An output signal and/or an interrupt signal may be generated that indicates a change in the detected energy level of the Ethernet link. Power may be provided to the circuitry that generates the output signal and the interrupt signal.

Cable sense mode for intelligent power saving in absence of link pulse

Certain embodiments of a method and system for safe and efficient power down and drawing minimal current when a device is not enabled may comprise receiving within a network adapter chip (NAC) a signal that indicates a reduced power mode. Based on this signal, the NAC may control an off-chip voltage source that provides reduced voltage to circuitry within the NAC. The off-chip voltage source, which may comprise a first PNP transistor and a second PNP transistor, may reduce a voltage to a first voltage and a second voltage. The NAC may also reduce current through the off-chip voltage source to approximately zero amperes and an output voltage of the off-chip voltage source to approximately zero volts. The first voltage and/or the second voltage may be fed back to control the output voltage and current of the off-chip voltage source.

Method and system for safe and efficient chip power down drawing minimal current when a device is not enabled

Aspects of the invention may be found in a method and system for testing an integrated circuit and may comprise an address selector, data selector and staging register coupled to a signal generator. The address selector may comprise a direct access memory test (DAMT) mode address control input and one or more output address pins coupled to an embedded memory device under test (DUT). The data selector may be coupled to at least one data pin and control pin of the signal generator and may comprise a DAMT mode data control input and at least one data output coupled to embedded memory DUT. A staging register comprising a first output clock rate which is one-quarter (&#xbc;) its input clock rate and matches a DUT burst write frequency may be coupled to an input of the data selector. A DAMT mode control may configure the memory DUT for DAMT operation.

Method and system for direct access memory testing of an integrated circuit

Certain embodiments for reducing instruction storage space for a processor integrated in a network adapter chip may include generating MIPS instructions from corresponding new instructions. The new instructions may be in patch code instruction (PCI) format. The new instructions may be decoded and the MIPS instructions may be generated by a MIPS processor within a network adapter chip. Decoding the new instructions may also be referred to as interpreting the new instructions. The new instructions may comprise fewer bits than the generated MIPS instructions. The generated MIPS instructions may be executed by the MIPS processor within the network adapter chip.

Method and system for reducing instruction storage space for a processor integrated in a network adapter chip

Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without initiation by a central processing unit (CPU). The resetting may occur via a virtual CPU. The CPU and the virtual CPU may be integrated on a single chip. The signal generation and EEPROM resetting may occur via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

Method and system for hardware implementation of resetting an external two-wired EEPROM

Certain aspects of the invention for packet segmentation and offload may comprise determining whether an identified packet is a large send offload packet (LSOP). If the identified packet is a LSOP, a selection may be made between a hardware process and a firmware process for handling the LSOP. The LSOP may then be processed by the selected hardware process or firmware process. At least a portion of protocol header information for a first segment of the LSOP may be stored and subsequently utilized for at least a header portion of a second segment of the LSOP. A payload corresponding to the second segment of the LSOP may be placed at a determined offset within a transmit buffer for the second segment. A header portion of the second segment may be updated based on at least a header portion of a previous segment.

Certain embodiments of an extreme power down mode for extreme power savings when no network presence is detected may comprise disabling at least one device driver for at least one hardware device in a network adapter chip. The device driver may be disabled prior to disabling the hardware device upon starting a power reduction mode for the network adapter chip. The device driver for the hardware device on the network adapter chip may be enabled after enabling the hardware device upon ending a power reduction mode for the network adapter chip. The hardware device may be disabled by reducing power to it. Similarly, power may be provided to the hardware device to enable it. The network adapter chip may be reset to enable the hardware device upon providing power to the hardware device so that the hardware device may be at a known state.

Certain embodiments for a self-booting Ethernet controller chip (NAC) may comprise a processor within the NAC that determines whether legacy boot code is present in memory external to the NAC. If legacy boot code is present in the external memory, the NAC may boot from the legacy boot code. If the legacy boot code is not present in the external memory, the processor may boot the NAC from the self-boot code in the ROM within the NAC. The processor may also read network configuration data from the external memory. The network configuration data may be stored, for example, in a NVRAM. The processor may copy the network configuration data from the NVRAM to a RAM within the NAC while booting.

Method and system for a self-booting Ethernet controller

Methods for identifying devices may include receiving by one or more memory devices, one or more of a plurality of read memory device ID commands. The one or more memory devices may respond to the received one or more of the plurality of read memory device ID commands. The response may include identification information corresponding to the one or more memory devices. The one or more of a plurality of read memory device ID commands may correspond to one or more of a plurality of supported memory devices. At least one access protocol may be utilizing for performing reading, erasing, and/or writing to the one or more memory devices, if the response identifies the one or more memory devices as one of the one or more of the plurality of supported memory devices.

Automatically detecting types of external data flash devices

Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

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Dublin, CA, United States of America

Jonathan Fuchuen Lee