Provigent Ltd.

Centipede Semi Ltd.

Maxlinear Asia Singapore Pte Ltd

Broadcom Semiconductors Israel Ltd.

Broadcom Corporation

Speedata Ltd.

Baby Patent Ltd.

Jonathan Friedmann

Noam Mizrahi

Alberto Mandler

Shay Koren

Igal Kushnir

Ronen Shaked

Ahikam Aharony

Ronen Yonesi

James D Bennett

Zohar Montekyo

Ehud Ashkenazi

Ran Sofer

Ragfi Ravid

Tzahi Oren

Eran Ridel

Kobi Sturkovich

Yoav Etsion

Dani Voitsechov

Amir Eliaz

Evgeni Krimer

Igal (Yehuda) Kushnir

Rafi Ravid

Oren Shrak

Alon Shavit

Moshe Penso

Ahikam Ahrony

Yoram Gorsetman

Ido Goren

Avi Turgeman

A processor includes a compute fabric and a controller. The compute fabric includes an array of compute nodes and interconnects that configurably connect the compute nodes. The controller is configured to receive at least first and second different Data-Flow Graphs (DFGs), each specifying code instructions, and to configure at least some of the compute nodes and interconnects in the compute fabric to concurrently execute the code instructions specified in the first and second DFGs, and send to the compute fabric multiple first threads that execute the code instructions specified in the first DFG and multiple second threads that execute the code instructions specified in the second DFG, thereby causing the compute fabric to execute, at least during a given time interval, both code instructions specified in the first DFG and code instructions specified in the second DFG.

Coarse-grain reconfigurable array processor with concurrent handling of multiple graphs on a single grid

An advanced split microwave architecture is provided. The advanced split microwave architecture includes a smart outdoor communication unit including a digital N-Plexer configured to multiplex and/or demultiplex a received data signal in the digital domain, a processor unit configured to carry out instructions to control operation of the digital N-Plexer, and a converter module configured to convert the received data signal between the digital domain and the analog domain. The smart outdoor communication unit further includes an RF module, having digital capabilities, configured to correct errors within the received data signal in the digital domain, perform a conversion of the received data signal, to amplify a power of the received data signal, and to perform automatic gain control in the digital domain.

Split microwave backhaul architecture with smart outdoor unit

A method which includes, in a processor that processes instructions of program code, processing one or more of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions at least partially in parallel with processing of the instructions by the first hardware thread.

Parallelized execution of instruction sequences

A method which includes, in a processor that processes instructions of program code, processing one or more of the instructions in a first segment of the instructions by a first hardware thread. Upon detecting that an instruction defined as a parallelization point has been fetched for the first thread, a second hardware thread is invoked to process at least one of the instructions in a second segment of the instructions, at least partially in parallel with processing of the instructions of the first segment by the first hardware thread, in accordance with a specification of register access that is indicative of data dependencies between the first and second segments.

Parallelized execution of instruction sequences based on pre-monitoring

A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. A relationship between the memory addresses accessed by two or more of the memory-access instructions is identified, based on respective formats of the memory addresses specified in the symbolic expressions. An outcome of at least one of the memory-access instructions is assigned to be served from an internal memory in the processor, based on the identified relationship.

Processor with efficient memory access

A processor includes a processing pipeline including multiple hardware threads and configured to execute software code instructions that are stored in a memory, along with multiple registers, configured to be read and written to by the processing pipeline during execution of the instructions. A monitoring unit monitors the instructions in the processing pipeline and records respective monitoring tables indicating the registers accessed in processing the instructions in different sequences of the instructions, and parallelizes among the hardware threads of the processor, using the respective monitoring tables, execution of repetitions of at least first sequences of the instructions. The monitoring unit is configured to evaluate a termination criterion based on the monitored instructions while monitoring the processing and recording the respective monitoring tables, and upon meeting the termination criterion, to terminate the monitoring before completion of the recording of the respective monitoring tables for at least second sequences of the instructions.

Early termination of segment monitoring in run-time code parallelization

A communications network is disclosed that includes one or more microwave backhaul nodes for routing communications between one or more near end mobile communications devices and one or more far end mobile communications devices. The communications network includes a central monitoring and control infrastructure, a remote monitoring and control infrastructure and/or a local monitoring and control infrastructure. The central monitoring and control infrastructure, the remote monitoring and control infrastructure and/or the local monitoring and control infrastructure can directly manage the one or more microwave backhaul nodes. Alternatively, the remote monitoring and control infrastructure and/or the local monitoring and control infrastructure can indirectly manage the one or more microwave backhaul nodes through the central monitoring and control infrastructure.

Management of backhaul nodes in a microwave backhaul

A method includes, in a processor, processing a sequence of pre-compiled instructions by an instruction pipeline of the processor. A first block of instructions is identified in the instructions flowing via the pipeline. The first block includes a conditional branch instruction that conditionally diverges execution of the instructions into at least first and second flow-control traces that differ from one another in multiple instructions and converge at a given instruction that is again common to the first and second flow-control traces. A second block of instructions, which is logically equivalent to the first block but replaces the first and second flow-control traces by a single flow-control trace, is created by the processor at runtime. The pipeline is caused to execute the second block instead of the first block.

Hardware-based run-time mitigation of conditional branches

A method includes, in a processor that processes instructions of program code, processing a first segment of the instructions. One or more destination registers are identified in the first segment using an approximate specification of register access by the instructions. Respective values of the destination registers are made available to a second segment of the instructions only upon verifying that the values are valid for readout by the second segment in accordance with the approximate specification. The second segment is processed at least partially in parallel with processing of the first segment, using the values made available from the first segment.

Run-time parallelization of code execution based on an approximate register-access specification

A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. Based on respective formats of the memory addresses specified in the symbolic expressions, a sequence of load instructions that access a predictable pattern of memory addresses in the external memory is identified. At least one cache line that includes a plurality of data values is retrieved from the external memory. Based on the predictable pattern, two or more of the data values that are requested by respective load instructions in the sequence are saved from the cache line to the internal memory. The saved data values are assigned to be served from the internal memory to one or more instructions that depend on the respective load instructions.

Processor with efficient processing of recurring load instructions from nearby memory addresses

An advanced split ODU architecture is provided. The advanced architecture includes an indoor communication unit including a digital modem assembly configured to modulate and demodulate digital data, and also includes a digital interface module configured to transmit and/or receive the digital data, over a digital communication pathway, between the indoor communication unit and an external outdoor communication unit. The advanced architecture further includes an outdoor communication unit having a digital interface module configured to transmit and/or receive the digital data, over the digital communication pathway, between the outdoor communication unit and an external indoor communication unit, and also includes a digital to analog converter configured to convert the digital data to analog data and an analog to digital converter configured to convert the analog data to the digital data, and further includes an RF module configured to convert the analog data between a baseband and a radio frequency.

Communication pathway supporting an advanced split microwave backhaul architecture

A method includes, in a processor that executes instructions of program code, monitoring instructions of a repetitive sequence of the instructions that traverses a flow-control trace so as to construct a specification of register access by the monitored instructions. Based on the specification, multiple hardware threads are invoked to execute respective segments of the repetitive instruction sequence at least partially in parallel. Monitoring of the instructions continues in at least one of the segments during execution.

Run-time code parallelization with continuous monitoring of repetitive instruction sequences

A communication system includes first and second transmitters, which are coupled to transmit respective first and second Radio Frequency (RF) signals carrying first and second data over a wireless communication channel. The transmitters are coupled to select an operational mode from a group of operational modes and to operate in the selected operational mode. The group of the operational modes includes at least two of a protection mode, wherein the second transmitter serves as backup to the first transmitter, a spatial multiplexing mode, in which the first data is different from the second data and the first and second transmitters transmit simultaneously, and a beam-forming mode, in which the first data is identical to the second data, the second RF signal includes a phase-shifted replica of the first RF signal, and the first and second transmitters transmit simultaneously.

Multi-mode wireless communication link

A method includes, in a processor that executes instructions of program code, identifying a region of the code containing one or more segments of the instructions that are at least partially repetitive. The instructions in the region are monitored, and an approximate specification of register access by the monitored instructions is constructed for the region. Execution of the segments in the region is parallelized using the specification.

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Tel Aviv, Israel

Jonathan Friedmann