Cypress Semiconductor Corporation

Jonathan F Churchill

Neil P Raftery

Cathal G Phelan

Ashish Pancholy

Mark A Finn

Thomas M Surrette

Jeyakumar Shanmugam

Colin J Hendry

James W Lutley

Kenneth A Maher

Mathew R Arcoleo

Gary Austin Gibbs

Raymond M Leong

Derek R Johnson

Sean Smith

Jeffrey F Kooiman

In one embodiment, a power on reset circuit includes a main circuit and a translation circuit. The main circuit may be configured to receive an external signal and to generate an input signal that is indicative of a state of the external signal. The translation circuit may be configured to receive the input signal and provide a power on reset signal indicative of a brownout condition of the external signal. The external signal may be a relatively high voltage signal compared to the power on reset signal.

Power on reset circuits

In one embodiment, a schematic for a net includes a load and a load schematic. The load schematic may include a parasitic on the net, and an equivalent of the load. A buffer may be employed to couple the load schematic to the schematic. Among other advantages, this simplifies comparison of parasitics between the schematic and a corresponding layout.

Verification of integrated circuit designs using buffer control

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to (i) a clock signal and (ii) one or more second control signals. The second circuit may be (i) coupled to the first circuit via one or more path circuits and (ii) configured to present an output signal in response to the one or more first control signals. All of the one or more first control signals may have a preferred edge skew.

Dual tristate path output buffer control

An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii), a don't care state.

Wired address compare circuit and method

A method for stress testing a memory array comprising the steps of (A) setting all memory cells in the memory array to a first digital state, (B) selecting all blocks of the memory array and (C) setting all wordlines in the memory array to a second digital state.

Wordline and pseudo read stress test for SRAM

A system and method are disclosed herein for leakage testing of a static random access memory (SRAM) semiconductor memory device. Subtle leakage defects may be present in some devices in the early stages of SRAM production. These defects may later result in hard failures when packaged devices are burned in, but are not detected by functional tests performed during wafer sort. The leakage defects are associated with complementary bit line pairs within the SRAM matrix, and may be revealed by leakage current measurements made between all of the complementary bit line pairs within the SRAM. Comparatively minor modifications to the internal circuitry of the SRAM enable the leakage measurements to be performed during wafer sort, so defective devices can be screened out prior to packaging, lead-bonding, etc.

Direct bit line-bit line defect detection test mode for SRAM

An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii) a high-Z state.

A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.

Scan path circuitry including a programmable delay circuit

A circuit for generating a pulse including a scan register having a first scan bit; first logic device receiving a first signal and generating a second signal; and a programmable delay circuit coupled to the scan register and the first logic device. The programmable delay circuit receives the second signal and generates a delayed second signal after a programmable period of time. The programmable period of time is determined by the first scan bit. The circuit also includes a logic circuit that recevies the second signal and the delayed second signal. The logic circuiit outputs the pulse having a pulse width proportional to the programmable period of time.

Scan path circuitry for programming a variable clock pulse width

An integrated circuit including a first input for receiving a scan enable control signal and a second input for receiving a test mode control signal. The integrated circuit also includes a programmable scan circuit coupled to the first input and the second input. The programmable scan circuit configures the integrated device to operate in a default mode, a scan mode, or a test mode in response to the scan enable and test mode control signals.

Test mode features for synchronous pipelined memories

A circuit including a register coupled to a control circuit. The register has a synchronous mode of operation and an asynchronous mode of operation. The a control circuit controls whether the register operates in the synchronous mode or the asynchronous mode. The circuit may further include a scan register having scan data. The control circuit may cause the register to operate in the synchronous or asynchronous mode in response to the scan data.

Scan path circuitry including an output register having a flow through

A dynamic voltage reference circuit for generating one or more control signals for use in controlling a delay circuit or other circuit that requires compensation for process variations. The control signals are generated without drawing DC current at times other than when the active edge is propagating through the delay circuit. As a result, a reference generator with reduced power consumption is realized.

Dynamic voltage reference which compensates for process variations

A Static Random Access Memory (SRAM) comprises an input/output pin and driver means connected to the input/output pin. The driver means are configured to drive the input/output pin to a voltage potential using a first current, and are further configured to hold the input/output pin at approximately the voltage potential using a second current. In one embodiment, the driver means may comprise a driver unit for driving the input/output pin to the voltage potential, a bus hold circuit for holding the input/output pin at the voltage potential and a control unit connected to the driver unit and the bus hold circuit. The control unit may activate and deactivate the driver unit and the bus hold circuit.

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Reading, United Kingdom

Jonathan F Churchill