Texas Instruments Corporation

Jonathan Elliot Bergsagel

Gregory Raymond Shurtz

Mihir Narendra Mody

Donald Edward Steiss

Charles Lance Fuoco

Sriramakrishnan Govindarajan

Sunita Nadampalli

Aishwarya Dubey

Brian Okchon Chae

Jason A T Jones

Anish Reghunath

Venkateswara Rao Mandela

Rajesh Kumar Vanga

Nishanth Menon

Thomas Ray Shelburne

Ian Carl Byers

Jason At Jones

In described examples, a method of operating a system on chip (SoC) includes the following steps. Receive a component description that describes connections among circuit elements of the SoC. Receive a list of specified peripherals to activate while the SoC boots. Receive a hint data that describes a bypass mode clock frequency of a phase locked loop (PLL) of the SoC. Determine an operational data in response to the component description, the hint data, and the specified peripherals. The operational data specifies a subset of the circuit elements required to make the specified peripherals operational. Initialize, and limit the initializing, to the subset of the circuit elements.

Integrated circuit with accelerated boot to priority function

In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

Real time input/output address translation for virtualized systems

An integrated circuit includes a display sub-system that has a plurality of image processing resources and control logic. The image processing resources include a plurality of image processing pipelines configured to operate in parallel, overlay logic coupled to receive image data from the plurality of image processing pipelines, and an image output port coupled to an output of the overlay logic with image data outputs configured to couple to one or more display devices. The control logic is dynamically configurable to assign each of the image processing resources to a selected one of a first control port and a second control port. The first control port is configured to be controlled exclusively by a first processor and the second control port is configured to be controlled exclusively by a second processor.

Display sub-system sharing for heterogeneous systems

An integrated fault-tolerant augmented area viewing system includes, for example, a subsystem processor for receiving a safety signal for blind spot monitoring from a blind spot sensor and for generating a subsystem processor video output signal in response to the received safety signal. Selector circuitry selects the subsystem processor video output signal or a master controller video output signal received from a master controller and generates a selected video output signal in response. The selector circuitry performs the selection of the video output signal selection in response to receiving a safety request signal generated in response to a user action. A buffer outputs the selected video output signal for displaying on a display for viewing by the user.

Integrated fault-tolerant augmented area viewing system

The present invention provides a solution that automatically detects and connects the properly terminated line pair and then allows modem training to proceed. The present invention can set a control parameter at the physical layer that establishes a training 'state' for the modem (). Training states can determine whether or not automatic line detection () is utilized. Automatic line detection () can be accomplished by measuring the power levels () on each of the line pairs () and then selecting the line pair () that has the highest power level measurement () as the line on which to continue training the modem (). The selected line pair () can be stored for use as the properly terminated line pair.

Automatic line pair detection in a modem

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Richardson, TX, United States of America

Jonathan Elliot Bergsagel