Inmos Limited

Stmicroelectronics Gmbh

Jonathan Edwards

Michael David May

David L Waller

Michael K Thompson

Richard N Campbell

A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Microcomputer with high density RAM on single chip

A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronization and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Microcomputer with high density RAM in separate isolation well on single

Microcomputer with high density ram in separate isolation well on single

A microcomputer includes an on-chip processor with at least 1K bytes of high density RAM on-chip together with isolation regions to protect the RAM from noise from transistors on-chip operating independently of the RAM.

A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks or microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

In a semi-conductor memory cell components are formed in regions separated from each other by one or more insulation layers (40) and first and second load resistors (20,22) and gate regions (70,72) of first and second cross-coupled driver field effect transistors (16,18) are formed in a first conductive layer (64) and the word line (36) and gate regions (66,68) of first and second transfer transistors (28,30) are formed in a second conductive layer (60).

Memory cell

A programmable, high speed, single chip microcomputer includes 4K of RAM, ROM, registers and an ALU. Program can be stored in the on-chip RAM. The first local variable of each process to be executed is a workspace pointer (WPTR), and each process has a respective workspace identified by its WPTR. For each process, addressing of other variables is relative to the current WPTR, which is stored in a workpiece pointer register (WPTR REG). Instructions are constant bit size, having a function portion and a data portion loaded, respectively, into an instruction buffer (IB) and an operand register (OREGTR). Memory address locations are formed by combining the contents of the workspace pointer register and the operand register, or the contents of the A Register and the operand register. A set of 'direct functions' obtains data from OREG. 'Indirect functions' use the OREG contents to identify other functions, obtaining data from registers other than the operand register. A 'prefixing' function (PFIX) develops operands having long bit lengths. Scheduling and descheduling of processes are achieved by forming a linked list within the several workspaces for the active processes. Each workspace identifies the workspace pointer of the next process to be executed. Each workspace contains in memory the identification of the next instruction to be executed for that respective process. A 'last pointer' register (LPTR REG.) cooperates in the scheduling operations. Each microcomputer chip can be coupled serially to other such chips on a respective pair of only two wires, each a unidirectional channel. Each channel also has two registers, one for process identification and one for data. Communications are synchronized.

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Bristol, United Kingdom

Jonathan Edwards