Intel Corporation

Jonathan E Schmidt

Chun Fung Man

Scott Nelson

Zion S Kwok

Steffen Kosinski

Joerg Hartung

Jack Cummings

Systems, apparatuses and methods may provide for firmware access wrapper technology that includes a plurality of input registers communicatively coupled to a hardware power controller, a plurality of output registers communicatively coupled to the hardware power controller, and a processor communicatively coupled to the input registers and the output registers. The processor may include configurable logic to identify a control policy change with respect to the hardware power controller, detect input signal information in one or more of the input registers, and conduct a modification of one or more values in the output registers based on the control policy change and the input signal information.

Hybrid hardware/firmware power management controller for media devices

Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for dividing error correcting code ('ECC') codewords into portions and storing the portions among multiple die of non-volatile memory ('NVM'). For example, a device may include memory including a first die and a second die, and a memory controller configured to store a first portion of a codeword for use with an error correcting code in a first segment of the first die and to store a second portion of the codeword in a first segment of the second die. In various embodiments, the first segment of the second die may be offset from the first segment of the first die. Other embodiments may be described and/or claimed.

Storage of codeword portions

A device, method, machine-readable medium, and system are disclosed. In one embodiment the device is a memory controller capable of modifying a reference voltage to a persistent moving read reference (MRR) voltage level for use during one or more subsequent reads to a non-volatile memory array. This modification is in response to a change in a reference voltage supplying the non-volatile memory array from a previous reference voltage level to a temporary MRR voltage level.

Persistent moving read reference

In a non-volatile memory that reads a binary value from a storage cell by comparing the voltage level of a stored charge in that cell against a reference voltage, the accumulated errors in a range of memory locations may be analyzed to determined if there are more errors in one direction than the other (for example, more 0-to-1 errors than 1-to-0 errors). If so, the reference voltage may be adjusted up or down so that subsequent reads from that range may produce approximately the same number of errors in each direction. For multiple-bits-per-cell memories, where there are multiple reference voltages for each cell, each reference voltage may be adjusted separately by keeping track of the errors related to that particular threshold.

Adjustable read reference for non-volatile memory

In various embodiments, the reference voltage used for read operations in a non-volatile memory may be adjusted up or down in an attempt to read data from an area that previously produced at least one uncorrectable error. The direction and amount of this adjustment may be based on the number and direction of correctable errors in surrounding data.

Growing community of inventors

New Westminster, Canada

Jonathan E Schmidt