Seagate Technology Incorporated

Jonathan E Olson

Michael Richard Fabry

Chau Chin Low

Terry Junge

Kenneth J Altshuler

Tiang Fee Yin

Oscar Woo

Phillip S Wilhelm

Ronald Lee Watts

Choon An Aw

John Douglas Deibert

The present invention is a method for evaluating a multiplicity of data handling devices each having a sealed chamber with several interior surfaces. It uses an impurity chamber containing thousands of dispersed gas-borne particles that each contain a marker impurity that is substantially absent from all of the interior surfaces of at least one of the devices. That device is tested for vulnerability to external dust using the marker impurity.

Evaluating data handling devices by means of a marker impurity

Packaged surface mount (SMT) chips having matched top contacts and bottom contacts are stacked. Chip features are selected to provide the desired connectivity between chip layers with a greater ease of manufacture. In one embodiment, additional spacing and routing layers are optionally provided between layers. In another, chips are differentiated by optionally providing different conductor and/or nonvolatile cell configurations. In yet another, a minority of a substrate's contacts are configured for aligning with a dielectric region of a spacing layer or substrate to create very low capacitance signal paths between stacked chips.

Surface mount IC stacking method and device

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Boulder, CO, United States of America

Jonathan E Olson