General Electric Company

Morpho Detection, Inc.

Jonathan David Short

James Wilson Rose

John Eric Tkaczyk

Wen Li

George E Possin

Brian David Yanoff

Jianjun Guo

Xiaoye Wu

Yanfeng Du

James Walter LeBlanc

Charles Gerard Woychik

Peter Michael Edic

Samit Kumar Basu

Biju Jacob

Aaron Judy Couture

Sergei Ivanovich Dolinsky

Christopher David Unger

Kent Charles Burr

Oliver Richard Astley

David Michael Hoffman

Bruno Kristiaan Bernard De Man

Mark Ernest Vermilyea

Ching-Yeu Wei

Clark Alexander Bendall

David Leo McDaniel

Robert Gideon Wodnicki

Abdelaziz Ikhlef

Peter Micah Sandvik

Naresh Kesavan Rao

Kevin Andrew Coombs

William Robert Ross

Loucas Tsakalakos

Ashutosh Joshi

Scott Stephen Zelakiewicz

Kevin Paul McEvoy

Ansas Matthias Kasten

J Eric Tkaczyk

Donna Marie Sherman

Sabarni Palit

Sora Kim

Martin Kinfei Lee

Ibrahim Issoufou Kouada

Joe James Lacey

Andrea Jeanne Howard

Michael James Palleschi

Rogerio Geraldes Rodrigues

Xingguang Zhu

In certain embodiments, a mixed signal integrated circuit is provided that includes both a digital portion and an analog portion. A shield is provided that overlays one of the digital portion or the analog portion of the mixed signal integrated circuit. The shield limits propagation of signals between the digital portion and the analog portion of the mixed signal integrated circuit.

Integrated shield structure for mixed-signal integrated circuits

Embodiments of a solid state photomultiplier are provided herein. In some embodiments, a solid state photomultiplier may include an epitaxial layer, a high voltage region formed in the epitaxial layer, a low voltage region formed in the epitaxial layer, and an intermediate region disposed between the high voltage region and low voltage region, wherein the high voltage region is electrically coupled to the low voltage region via the intermediate region, and wherein at least a portion of the epitaxial layer is disposed between the high voltage region and intermediate region and between the low voltage region and the intermediate region.

Solid state photomultiplier having an intermediate region coupled between high and low voltage regions and associated detector

Improved imaging systems are disclosed. More particularly, the present disclosure provides for an improved image sensor assembly for an imaging system, the image sensor assembly having an integrated photodetector array and its associated data acquisition electronics fabricated on the same substrate. By integrating the electronics on the same substrate as the photodetector array, this thereby reduces fabrications costs, and reduces interconnect complexity. Since both the photodiode contacts and the associated electronics are on the same substrate/plane, this thereby substantially eliminates certain expensive/time-consuming processing techniques. Moreover, the co-location of the electronics next to or proximal to the photodetector array provides for a much finer resolution detector assembly since the interconnect bottleneck between the electronics and the photodetector array is substantially eliminated/reduced. The co-location of the electronics next to or proximal to the photodetector array also enables/facilitates programmable pixel configuration for optimal image quality.

Integrated diode DAS detector

An imager tile including four-side buttable sub-imager pixel arrays with on-chip digitizing electronic readout circuit. Pixel groupings formed from among the plurality of imagers. Readout electronics including a buffer amplifier for each of the pixel groupings are connected to respective outputs of buttable imagers. Shared analog front ends connect to respective buffer amplifiers of pixel groupings. An analog-to-digital converter at a common centroid location relative to the shared analog front ends includes three data lines&#x2014;selection input/output line to individually select an output, a clock input line, and a shared digital output line. A pixel output from a respective buffer amplifier is addressable by data provided on the selection input/output line, and the pixel output is provided on the shared digital output line. The I/O lines connected to a programmable logic device where the imager serial data input is output as a massively parallel data stream.

Digital readout architecture for four side buttable digital X-ray detector

Embodiments of a solid state photomultiplier are provided herein. In some embodiments, a photosensor may include a sensing element; and readout electronics, wherein the sensing element is AC coupled to the readout electronics. In some embodiments, a solid state photomultipler may include a microcell having; a sensing element; and readout electronics, wherein the sensing element is AC coupled to the readout electronics.

Solid state photomultiplier

An imager including sub-imager pixel arrays having a plurality of four-side buttable imagers distributed on a substrate and an on-chip digitizing readout circuit. Pixel groupings formed from among the plurality of four-side buttable imagers. The readout electronics including a buffer amplifier for each of the pixel groupings and connected to respective outputs of each four-side buttable imager of the pixel grouping. A plurality of shared analog front ends, each shared analog front end connected to respective multiple buffer amplifiers from among the plurality of pixel groupings. An analog-to-digital converter located at a common centroid location relative to the plurality of shared analog front ends, the analog-to-digital converter having a fully addressable input selection to individually select an output from each of the plurality of shared analog front ends. An output of the analog-to-digital converter connected to a trace on a back surface of the wafer substrate by a through-substrate-via.

Universal four-side buttable digital CMOS imager

An embedded imaging system in one embodiment includes an encoding module, an imaging module, and a cable. The encoding module is disposed proximate to a proximal end of the system, and is configured to encode frame synchronizing information into timing information comprising a reference clock. The imaging module is disposed proximate the distal end, and includes an image capture device configured to obtain imaging information and a decoding module. The decoding control module is configured to obtain the timing information, to decode the timing information to obtain recovered frame synchronizing information, and to control the image capture device using the recovered frame synchronizing information. The cable is interposed between the proximal end and the distal end, and is configured for passage therethrough of the timing information and the imaging information.

Systems and methods for embedded imaging clocking

Embodiments of a photodiode array are provided herein. In some embodiments, a photodiode array may include a semiconductor layer configured to convert photons into analog electrical signals; and a passive layer having a first surface and a second surface disposed opposite the first surface, wherein the semiconductor layer is coupled to the first surface, and wherein the passive layer is configured to have a signal receiving component coupled directly to the second surface of the passive layer.

Photodiode array for imaging applications

A method for forming a sensor stack is presented. The method includes providing a substrate having a first side and a second side. Furthermore, the method includes disposing an integrated circuit having a first side and a second side on the first side of the substrate, where the integrated circuit comprises a first plurality of contact pads disposed on the first side of the integrated circuit. The method also includes providing a sensor array having a plurality of sensor elements, wherein each of the sensor elements has a first side and a second side, and wherein the sensor array comprises a second plurality of contact pads disposed on the second side of the sensor array. Furthermore, the method includes disposing an interposer having one or more interposer elements and one or more through vias disposed therethrough between the one or more sensor elements of the sensor array and the integrated circuit to raise the sensor array away from the first side of the integrated circuit such that a plane of the one or more sensor elements is locally normal to a sensor stack normal, wherein the interposer is configured to operationally couple the second side of the sensor elements in the sensor array to the first side of the integrated circuit. In addition, the method includes operationally coupling the first plurality of contact pads on the first side of the integrated circuit to a second plurality of contact pads on the second side of the sensor array to form a tileable sensor stack.

Detector array with a through-via interposer

An apparatus for reducing photodiode thermal gain coefficient includes a bulk semiconductor material having a light-illumination side. The bulk semiconductor material includes a minority charge carrier diffusion length property configured to substantially match a predetermined hole diffusion length value and a thickness configured to substantially match a predetermined photodiode layer thickness. The apparatus also includes a dead layer coupled to the light-illumination side of the bulk semiconductor material, the dead layer having a thickness configured to substantially match a predetermined thickness value and wherein an absolute value of a thermal coefficient of gain due to the minority carrier diffusion length property of the bulk semiconductor material is configured to substantially match an absolute value of a thermal coefficient of gain due to the thickness of the dead layer.

Apparatus for reducing photodiode thermal gain coefficient

Apparatus for reducing photodiode thermal gain coefficient and method of making same

A scintillator array and method for making the same are provided. The array comprises a bi-layer reflector further comprising a conformal smoothing layer and a mirror layer. The bi-layer reflector does not comprise an intervening reducing agent or adhesion layer and/or comprises aluminum. Further, the mirror layer may be deposited via gas phase metallization, allowing application to tightly confined spaces. A detector array comprising the scintillator array is also provided.

Scintillator arrays and methods of making the same

A CT detector includes a direct conversion material configured to generate electrical charge upon reception of x-rays, a plurality of metallized anodes configured to collect electrical charges generated in the direct conversion material, at least one readout device, and a redistribution layer having a plurality of electrical pathways configured to route the electrical charges from the plurality of metallized anodes to the at least one readout device. A plurality of switches is coupled to the plurality of electrical pathways between the plurality of metallized anodes and the at least one readout device, wherein each of the plurality of switches includes an input line electrically coupled to one of the plurality of metallized anodes, a first output node electrically coupled to the at least one readout device, and a second output node electrically coupled to at least one other switch of the plurality of switches.

Method and apparatus for flexibly binning energy discriminating data

An energy-sensitive computed tomography system is provided. The energy-sensitive computed tomography system includes an X-ray source configured to emit an X-ray beam resulting from electrons impinging upon a target material. The energy-sensitive computed tomography system also includes an object positioned within the X-ray beam. The energy-sensitive computed tomography system further includes a detector configured to receive a transmitted beam of the X-rays through the object. The energy-sensitive computed tomography system also includes a filter having an alternating pattern disposed between the X-ray source and the detector, the filter configured to facilitate measuring projection data that can be used to generate low-energy and high-energy spectral information.

System and method for energy sensitive computed tomography

A diagnostic imaging system includes an x-ray source that emits a beam of x-ray energy toward an object to be imaged and an energy discriminating (ED) detector that receives the x-ray energy emitted by the x-ray energy source. The ED detector includes a first layer having a first thickness, wherein the first layer comprises a semiconductor configurable to operate in at least an integrating mode and a second layer having a second thickness greater than the first thickness, and configured to receive x-rays that pass through the first layer. The system further includes a data acquisition system (DAS) operably connected to the ED detector and a computer that is operably connected to the DAS. The computer is programmed to identify saturated data in the second layer and substitute the saturated data with non-saturated data from a corresponding pixel in the first layer.

Method and system of energy integrating and photon counting using layered photon counting detector

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Saratoga Springs, NY, United States of America

Jonathan David Short