International Business Machines Corporation

Globalfoundries Inc.

Morton International, Inc.

Jonathan Daniel Chapple-Sokol

Richard Anthony Conti

William Joseph Murphy

James Anthony O'Neill

Timothy Dooling Sullivan

Thomas L McDevitt

Manu J Tejwani

Narayana V Sarma

Jeffrey P Gambino

Jed Hickory Rankin

Terence B Hook

Baozhen Li

Randy William Mann

Tom C Lee

Steven G Barbee

Seshadri Subbanna

Daniel Scott Vanslette

Jeffrey Scott Zimmerman

Justin W Wong

Tina J Cotler

Christopher A Ponsolle

Bette B Reuter

Anthony K Stamper

Charles W Koburger, Iii

Zhong-Xiang He

Kirk David Peterson

Richard Hsiao

Edward Crandal Cooney, Iii

James Spiros Nakos

David Edward Kotecki

David C Thomas

Michael James Lercel

Jyothi Singh

Keith Edward Downes

Michael L Passow

Daniel A Delibac

Donald L Wilson

Steven Paul Zuhoski

Donald Leslie Wilson

Steven P Barkyoumb

David V Horak

Louis L Hsu

Michael S Barnes

Andrew Herbert Simon

John Joseph Pekarik

Michael Jay Shapiro

John H Keller

Robert Michael Geffken

James Allan Bruce

Paul J Tsang

Cathryn Jeanne Christiansen

Paul M Feeney

Shawn A Adderly

Chi-Min Yuan

Karen Lynne Holloway

Mark P Murray

William M Holber

Paul F Seidler

Justin Wai-Chow Wong

Ben C Hui

Dragan Podlesnik

John Joseph Prxarik

James Allen Bruce

Ravi Kanjolia

Approaches for providing a liner at a via-to-wire interface are provided. A method includes: forming a via opening that exposes an upper surface of a copper wire; forming a titanium liner on the upper surface of the wire; forming a tungsten liner on the titanium liner; and forming a via on the second liner in the via opening.

Titanium tungsten liner used with copper interconnects

Embodiments of the present invention provide a method for achieving uniform capacitance between a semiconductor wafer and an electrostatic chuck. In certain embodiments, the method comprises the step of forming a layer on a first side of the semiconductor wafer, wherein the layer has a specified resistivity. The method further comprises placing the semiconductor wafer on the electrostatic chuck, wherein the layer contacts the electrostatic chuck. The method further comprises applying a radio frequency signal to the electrostatic chuck, and processing a second side of the semiconductor wafer.

Achieving uniform capacitance between an electrostatic chuck and a semiconductor wafer

A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAlliner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAlliner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAlliner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

Electromigration resistant aluminum-based metal interconnect structure

A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.

Metal seed layer deposition

A structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing

A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

A method of ensuring against deterioration of an underlying silicide layer over which a refractory material layer is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is realized by first providing a continuous polysilicon layer prior to the refractory material deposition. The continuous polysilicon layer, preferably no thicker than 50 &angst;, serves a sacrificial purpose and prevents interaction between any fluorine that is released during the refractory material deposition step from interacting with the underlying silicide.

Method of forming refractory metal contact in an opening, and resulting structure

A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.

Borderless contact to diffusion with respect to gate conductor and methods for fabricating

A method and structure is described which improves the manufacturability of integrated circuit interconnect and stud contacts in contact with semiconductor substrates and upper levels of metallization. The monolithic structure is formed from a thick layer of refractory metal. A variation in the monolithic structure is in the use of a dual damascene local interconnect portion of the structure which allows the local interconnect to pass over structures previously formed on the substrate.

Metallurgy for semiconductor devices

A method and apparatus for monitoring and controlling reactant vapors prior to chemical vapor deposition (CVD). The reactant vapors are monitored at full concentration without sampling as they are transported to a CVD reactor. Contaminants detected cause a process controller to switch the transport path to direct reactant vapors to a system pump.

Method of aluminum oxide low pressure chemical vapor deposition (LPCVD)

A process and apparatus for Al.sub.2 O.sub.3 CVD on silicon wafers using aluminum tri-isopropoxide in a high-volume production environment is presented. The conditions required to use ATI in a production environment and provide maximum utilization of ATI are first of all delivery of ATI via direct evaporation. The ATI source bottle is pumped out (bypassing substrates) until propene and isopropanol signals are reduced to 1% of process pressure before start of aluminum oxide deposition. Either IR spectroscopy or mass spectrometry can be used to provide a control signal to the microprocessor controller. Heating the supplied tetramer to 120.degree. C. for two hours assures complete conversion to trimer. The ATI is stored at 90.degree. C. to minimize decomposition during idle periods and allow recovery of trimer upon return to 120.degree. C. for two hours. During periods of demand, the ATI is held at 120.degree. C. to minimize decomposition.

Aluminum oxide LPCVD system

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Essex Junction, VT, United States of America

Jonathan Daniel Chapple-Sokol