Intel Corporation

Jonathan D Pearce

Elmoustapha Ould-Ahmed-Vall

Murali Ramadoss

Ben J Ashbaugh

Vikranth Vemulapalli

David B Sheffield

Altug Koker

Subramaniam M Maiyuran

Aravindh V Anantaraman

Valentin Andrei

Sungye Kim

Jeffrey J Cook

William B Sadler

Abhishek R Appu

Joydeep Ray

Nicolas C Galoppo Von Borries

Mike MacPherson

Deborah T Marr

Srikanth T Srinivasan

Asit K Mishra

Robert Valentine

Mark Jay Charney

Varghese George

Prasoonkumar Surti

Edward Thomas Grochowski

Eriko Nurvitadhi

Vasanth Ranganathan

Kamal Sinha

Scott R Janus

Lakshminarayanan Striramassarma

Brent E Insko

Arthur Hunter, Jr

Marian Alin Petre

Andrey Ayupov

Gilbert A Neiger

Christopher J Hughes

Jesus Corbal

Rajesh M Sankaran

Koichi Yamada

Thomas D Fletcher

Joseph Nuzman

Stephen R Van Doren

Lokpraveen B Mosur

Paul Caprioli

Dennis Ryan Bradford

Narayan Ranganathan

Kent D Glossop

Niall D McDonnell

Richard J Greco

Ganesh Venkatesh

Dwight P Manley

Tracy Garrett Drysdale

Nicholas P Carter

Michael A O'Hanlon

Abhijit Davare

Anton Alexandrovich Sorokin

Guei-Yuan Lueh

Milind Baburao Girkar

Pattabhiraman K

Ehud Cohen

Jesus Corbal San Adrian

Yoav Harel

Steven Burns

Desmond A Kirkpatrick

Shailesh Shah

Alexander F Heinecke

Raanan Sade

Dan Baum

Jorge E Parra

Ronen Zohar

Michael J Espig

Jaewoong Sim

Krishna N Vinod

Debbie Marr

Nicolas Galappo Von Borries

Rishiraj A Bheda

Niran Cooray

Shreesha Srinath

Ching-Kai Liang

Niall D Mcdonnell

Michael A O'HANLON

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

Systems and methods for improving cache efficiency and utilization

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Scalar core integration

Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

Data prefetching for graphics data processing

Disclosed embodiments relate to systems and methods for performing nibble-sized operations on matrix elements. In one example, a processor includes fetch circuitry to fetch an instruction, decode circuitry to decode the fetched instruction the fetched instruction having fields to specify an opcode and locations of first source, second source, and destination matrices, the opcode to indicate the processor is to, for each pair of corresponding elements of the first and second source matrices, logically partition each element into nibble-sized partitions, perform an operation indicated by the instruction on each partition, and store execution results to a corresponding nibble-sized partition of a corresponding element of the destination matrix. The exemplary processor includes execution circuitry to execute the decoded instruction as per the opcode.

Systems and methods for performing nibble-sized operations on matrix elements

Embodiments are generally directed to thread group scheduling for graphics processing. An embodiment of an apparatus includes a plurality of processors including a plurality of graphics processors to process data; a memory; and one or more caches for storage of data for the plurality of graphics processors, wherein the one or more processors are to schedule a plurality of groups of threads for processing by the plurality of graphics processors, the scheduling of the plurality of groups of threads including the plurality of processors to apply a bias for scheduling the plurality of groups of threads according to a cache locality for the one or more caches.

Thread group scheduling for graphics processing

Methods and apparatus relating to predictive page fault handling. In an example, an apparatus comprises a processor to receive a virtual address that triggered a page fault for a compute process, check a virtual memory space for a virtual memory allocation for the compute process that triggered the page fault and manage the page fault according to one of a first protocol in response to a determination that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the compute process, or a second protocol in response to a determination that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the compute process. Other embodiments are also disclosed and claimed.

Preemptive page fault handling

An apparatus and method for performing efficient, adaptable tensor operations. For example, one embodiment of a processor comprises: front end circuitry to schedule matrix operations responsive to a matrix multiplication instruction; a plurality of lanes to perform parallel execution of the matrix operations, wherein a lane comprises an arithmetic logic unit to multiply a block of a first matrix with a block of a second matrix to generate a product and to accumulate the product with a block of a third matrix, and wherein the matrix blocks are to be stored in registers within the lane; and broadcast circuitry to broadcast one or more invariant matrix blocks to at least one of different registers within the lane and different registers across different lanes.

Apparatus and method for adaptable and efficient lane-wise tensor processing

Embodiments detailed herein relate to reduction operations on a plurality of data element values. In one embodiment, a process comprises decoding circuitry to decode an instruction and execution circuitry to execute the decoded instruction. The instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, where each index of the plurality of indices maps to one unique data element position of the first input register. The execution includes to identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register.

Method and apparatus for performing reduction operations on a plurality of associated data element values

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Hillsboro, OR, United States of America

Jonathan D Pearce