Intel Corporation

Jonathan D Combs

Jason W Brandt

Martin Licht

Michael W Chynoweth

Andrew Huang

Vikash Agarwal

Ahmad Yasin

Kameswar Subramaniam

Robert Valentine

Venkateswara Rao Madduri

Beeman C Strong

Stephen J Robinson

Corey D Gough

John M Esper

Asavari Paranjape

Thomas Madaelil

Khary Alexander

Andrew F Glew

Matthew C Merten

Hoichi Cheong

Ofer Levy

Robert T George

Sanjoy K Mondal

James Edward Phillips

Seth Abraham

Andreas Kleen

Rajshree Chabukswar

Christopher D Bryant

Maxim Loktyukhin

James D Allen

Benjamin C Chaffin

Jeffrey G Wiedemeier

Jonathan Jay Tyler

Peter J Ruscito

Julio Gago

Jonathan Y Tong

Kimberly C Weier

Angela D Schmid

Zia Ansari

Kevin B Smith

Anthony Wojciechowski

Santhosh Srinath

Christopher Mark Chrulski

Mathew Lowes

Charlie J Hewett

Sundararajan Ramakrishnan

Charlie Hewett

Patrick Konsor

Joseph K Olivas

Vidisha Chirra

Daeho Seo

Michael Chynoweth

Martin J Licht

An embodiment of an integrated circuit may comprise a core and an instruction decoder communicatively coupled to the core to decode one or more instructions for execution by the core, where the instruction decoder includes two or more decode clusters in a parallel arrangement, and circuitry to offline a decode cluster of the two or more decode clusters. Other embodiments are disclosed and claimed.

Instruction decode cluster offlining

Systems, methods, and apparatuses for power efficient generation of length markers for a variable length instruction set are described. In one embodiment, a hardware processor core includes a decoder circuit to decode instructions into decoded instructions, an execution circuit to execute the decoded instructions, an instruction cache, an instruction length decoder circuit, a predecode cache comprising a predecode bit, for each section of multiple sections of instruction data, that indicates when that section is identified as an end boundary of a variable length instruction, an incomplete decode table comprising a bit, for each proper subset of sections of instruction data, that indicates when that proper subset of sections has one or more invalid predecode bits in the predecode cache; and a fetch circuit to, for an incoming address of instruction data, perform a lookup in the instruction cache and the incomplete decode table, and, when there is a hit in the instruction cache for the instruction data at the incoming address and a hit in the incomplete decode table that indicates a proper subset of sections of the instruction data for the incoming address has one or more invalid predecode bits in the predecode cache, causes the instruction length decoder circuit to generate one or more predecode bits for the proper subset of sections of the instruction data for the incoming address that has the one or more invalid predecode bits.

Circuitry and methods for power efficient generation of length markers for a variable length instruction set

Systems, methods, and apparatuses relating to circuitry to implement precise last branch record event logging in a processor are described. In one embodiment, a hardware processor core includes an execution circuit to execute instructions, a retirement circuit to retire executed instructions, a status register, and a last branch record circuit to, in response to retirement by the retirement circuit of a first taken branch instruction, start a cycle timer and a performance monitoring event counter, and in response to retirement by the retirement circuit of a second taken branch instruction, that is a next taken branch instruction in program order after the first taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a first entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.

Methods, systems, and apparatuses for precise last branch record event logging

Systems, methods, and apparatuses relating to circuitry to implement toggle point insertion for a clustered decode pipeline are described. In one example, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, and a toggle point control circuit to toggle between sending instructions requested for decoding between the first decode cluster and the second decode cluster, wherein the toggle point control circuit is to: determine a location in an instruction stream as a candidate toggle point to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster, track a number of times a characteristic of multiple previous decodes of the instruction stream is present for the location, and cause insertion of a toggle point at the location, based on the number of times, to switch the sending of the instructions requested for decoding between the first decode cluster and the second decode cluster.

Scalable toggle point control circuitry for a clustered decode pipeline

Techniques and mechanisms for determining a latency event to be represented in performance monitoring information. In an embodiment, circuit blocks of a pipeline experience respective latency events at variously times during tasks by the pipeline which service a workload. The circuit blocks send to an evaluation circuit of the pipeline respective event signals which each indicate whether a respective latency event has been detected. The event signals are communicated in parallel with at least a portion of the pipeline. In response to a trigger event in the pipeline, the evaluation circuit selects an event signal, based on relative priorities of the event signals, which provides a sample indicating a detected latency event. Based on the selected event signal, a representation of the indicated latency event in provided to latency event count or other value performance monitoring information. In another embodiment, different time delays are applied to various event signals.

Device, system and method for identifying a source of latency in pipeline circuitry

Systems, methods, and apparatuses relating to circuitry to implement scalable port-binding for asymmetric execution ports and allocation widths of a processor are described. In one embodiment, a hardware processor core includes a decoder circuit to decode instructions into sets of one or more micro-operations, an instruction decode queue to store the sets of one or more micro-operations, a plurality of different types of execution circuits that each comprise a respective input port and a respective input queue, and an allocation circuit comprising a plurality of allocation lanes coupled to the instruction decode queue and to the input ports of the plurality of different types of execution circuits, wherein the allocation circuit is to, for an input of micro-operations on the plurality of allocation lanes, generate a sorted list of occupancy of the input queues of each input port, generate a pre-binding mapping of the input ports of the plurality of different types of execution circuits to the plurality of allocation lanes in a circular order according to the sorted list, when a type of micro-operation from an allocation lane does not match a type of execution circuit of an input port in the pre-binding mapping, slide the pre-binding mapping so that the input port maps to a next allocation lane having a matching type of micro-operation to generate a final mapping of the input ports of the plurality of different types of execution circuits to the plurality of allocation lanes, and bind the input ports of the plurality of different types of execution circuits to the plurality of allocation lanes according to the final mapping.

Methods, systems, and apparatuses for scalable port-binding for asymmetric execution ports and allocation widths of a processor

Techniques and mechanisms for providing branch prediction information to facilitate instruction decoding by a processor. In an embodiment, entries of a branch prediction table (BTB) each identify, for a corresponding instruction, whether a prediction based on the instruction (if any) is eligible to be communicated, with another prediction, in a single fetch cycle. A branch prediction unit of the processor determines a linear address of a fetch region which is under consideration, and performs a search of the BTB based on the linear address. A result of the search is evaluated to detect for any hit entry which indicates a double prediction eligibility. In another embodiment, where it is determined that double prediction eligibility is indicated for an earliest one the instructions represented by the hit entries, multiple predictions are communicated in a single fetch cycle.

Device, method and system for provisioning a real branch instruction and a fake branch instruction to respective decoders

Systems, methods, and apparatuses relating to circuitry to implement out-of-order access to a shared microcode sequencer by a clustered decode pipeline are described. In one embodiment, a hardware processor core includes a first decode cluster comprising a plurality of decoder circuits, a second decode cluster comprising a plurality of decoder circuits, a fetch circuit to fetch a first block of instructions and send the first block of instructions to the first decode cluster for decoding, and fetch a second block of instructions younger in program order than the first block of instructions and send the second block of instructions to the second decode cluster for decoding, a microcode sequencer comprising a memory that stores a plurality of micro-operations, and an arbitration circuit to arbitrate access by the first decode cluster and the second decode cluster to a shared read port of the memory, wherein the arbitration circuit is to allow the second decode cluster decoding the second block of instructions access to the shared read port of the memory instead of the first decode cluster decoding the first block of instructions when an instruction of the second block of instructions has a number of corresponding micro-operations in the microcode sequencer below an arbitration threshold.

Methods, systems, and apparatuses for out-of-order access to a shared microcode sequencer by a clustered decode pipeline

An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.

Branch type logging in last branch registers

Embodiments of an invention for a physical register table for eliminating move instructions are disclosed. In one embodiment, a processor includes a physical register file, a register allocation table, and a physical register table. The register allocation table is to store mappings of logical registers to physical registers. The physical register table is to store entries including pointers to physical registers in the mappings. The number of entry locations in the physical register table is less than the number of physical registers in the physical register file.

Physical register table for eliminating move instructions

Embodiments disclosed herein provide for monitoring performance of a processing device to manage non-precise events. A processing device includes a performance counter to track a non-precise event and to increment upon occurrence of the non-precise event, wherein the non-precise event comprises a first type of performance event that is not linked to an instruction in an instruction trace. The processing device also includes a first handler circuit to generate and store a first record, the first record comprising architectural metadata defining a state of the processing device at a time of generation of the first record, wherein the first handler circuit to generate records corresponding to precise events. The processing device further includes a second handler circuit communicably coupled to the first handler circuit, the second handler circuit to cause the first handler circuit to generate a second record for the non-precise event upon overflow of the performance counter.

Monitoring performance of a processing device to manage non-precise events

A processor includes a back end to execute decoded instructions and a front end. The front end includes two decode clusters and circuitry to receive data elements representing undecoded instructions, in program order, and to direct subsets of the data elements to the decode clusters. An IP generator directs one subset of data elements to the first cluster, detects a condition indicating that a load balancing action should be taken, and directs a subset of data elements immediately following the first subset in program order to the first or second decode cluster dependent on the action taken. The action may include annotating a BTB entry, inserting a fake branch in the BTB, forcing a cluster switch, or suppressing a cluster switch. The detected condition may be a predicated taken branch or an annotation thereof, or a heuristic based on a queue state, a count of uops, or a latency value.

System and method for load balancing in out-of-order clustered decoding

Apparatuses, methods, and systems relating to memory disambiguation are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, an execution unit to execute the decoded instruction, a retirement unit to retire an executed instruction in program order, and a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction.

Apparatuses, methods, and systems for memory disambiguation

In one embodiment, a processor includes an instruction decoder to receive and decode an instruction having a prefix and an opcode, an execution unit to execute the instruction based on the opcode, and flag modification override logic to prevent the execution unit from modifying a flag register of the processor based on the prefix of the instruction.

Flag non-modification extension for ISA instructions using prefixes

Growing community of inventors

Austin, TX, United States of America

Jonathan D Combs