Ampere Computing LLC

Other

Intel Corporation

Jonathan Christopher Perry

Bret Leslie Toll

George Van Horn Leming, Iii

John Gregory Favor

Stephan Jourdan

Benjamin C Chaffin

Nagi Aboulenein

Zhongying Zhang

Mark Dechene

Manjunath Shevgoor

Sean Philip Mirkes

Jacob Daniel Morgan

Jason Anthony Bessette

Faruk Guvenilir

Chieh-Yu Lin

John Saint Tran

Benjamin Crawford Chaffin

Performing instruction fetch pipeline synchronization (IFPS) in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides multiple processors including a remote processor. The remote processor receives, from an issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) request indicating a request to invalidate an address translation, and subsequently receives an IFPS request from the issuing processor. The remote processor determines that any previously received TLBI requests including the most recent TLBI request have completed. Upon receiving the IFPS request, the remote processor determines that all instructions within a fetch pipeline portion that were potentially fetched using address translations older than the IFPS request have proceeded from the fetch pipeline portion of an instruction processing circuit to an execution pipeline portion of the instruction processing circuit. The remote processor then performs a data synchronization barrier (DSB) operation, and issues a synchronization acknowledgement to the issuing processor.

Performing instruction fetch pipeline synchronization (IFPS) in processor-based devices

Aspects disclosed include hardware micro-fused memory (e.g., load and store) operations. In one aspect, a hardware micro-fused memory operation is a single atomic memory operation performed using a plurality of data register operands, for example a load pair or store pair operation. The load pair or store pair operation is treated as two separate operations for purposes of renaming, but is scheduled as a single micro-operation having two data register operands. The load or store pair operation is then performed atomically.

Hardware micro-fused memory operations

A memory management unit (MMU) including a unified translation lookaside buffer (TLB) supporting a plurality of page sizes is disclosed. In one aspect, the MMU is further configured to store and dynamically update page size residency metadata associated with each of the plurality of page sizes. The page size residency metadata may include most recently used (MRU) page size data and/or a counter for each page size indicating how many pages of that page size are resident in the unified TLB. The unified TLB is configured to determine an order in which to perform a TLB lookup for at least a subset of page sizes of the plurality of page sizes based on the page size residency metadata.

Flexible storage and optimized search for multiple page sizes in a translation lookaside buffer

A data processing system includes a store datapath configured to perform tag checking in a store operation to a store address associated with a cache line in a memory. The store datapath includes a cache lookup circuit configured to pre-load a store cache line that is to be updated in the store operation, wherein the store cache line comprises the cache line in the memory to be updated in the store operation. The store datapath also includes a tag check circuit configured to compare a store address tag associated with the store address to a store operation tag associated with the store operation. The data processing system may include a load datapath configured to perform tag checking in a load operation from a load cache line in the memory by comparing a load address tag associated with the load address to a load operation tag associated with the load operation.

Method, apparatus, and system for run-time checking of memory tags in a processor-based system

An apparatus and method for early page address prediction. For example, one embodiment of a processor comprises: an instruction fetch circuit to fetch a load instruction; a decoder to decode the load instruction; execution circuitry to execute the load instruction to perform a load operation, the execution circuitry including an address generation unit (AGU) to generate an effective address to be used for the load operation; and early page prediction (EPP) circuitry to use one or more attributes associated with the load instruction to predict a physical page address for the load instruction simultaneously with the AGU generating the effective address and/or prior to generation of the effective address.

Apparatus and method for an early page predictor for a memory paging subsystem

Globe with stand

A self balancing air handling system for conditioning an interior space includes an air handling unit having an outlet for supplying conditioned air to the space, an entrance providing an access from an exterior space to the interior space, an air plenum surrounding said space, and an inlet for returning air from said plenum to said air handling unit wherein said air handling unit supplies said conditioned air under conditions providing a positive pressure differential at said entrance between the interior space and the exterior space thereby limiting infiltration air into the interior space.

Air handling system with self balancing air entrance door

Growing community of inventors

Santa Clara, CA, United States of America

Jonathan Christopher Perry