Synopsys, Inc.

Other

Avant&excl; Corporation

Jonathan Calvin White

Gary Bruce Lipton

Harry Clarkson Johnson, Iv

Chiu-Yu Ku

Mark Daniel Pogers

Jinsik Yun

Danny Chang

Lihhsing Ke

A system, method, and computer readable medium with instructions for verifying an original layout are disclosed. The original layout includes cells arranged in a cell hierarchy, front-end-of-line (FEOL) layers, and back-end-of-line (BEOL) layers. In one embodiment, a reduced layout is generated by trimming out cells below a top tier of the cell hierarchy and filtering out the FEOL layers. A text-based short check is executed on the reduced layout. Next, an augmented reduced layout is generated. The augmented reduced layout includes pin information for cells in a second tier connected to the top tier. An interconnectivity check is then executed on the augmented reduced layout based on a schematic for the circuit. Afterwards, a result (e.g., location of short or connectivity mismatch) based on at least one of the text-based short check and the interconnectivity check is outputted. A conventional LVS check may then be executed.

Circuit layout verification

A funeral service apparatus and method for implementing the funeral service apparatus is provided and includes an apparatus body having a hex wrench, a knife blade, a Phillips head screwdriver, a flat head screwdriver, a holy water containment vial, a committal sand containment vial, scissors, a tape measure having a measuring tape, a pen and a flashlight. The hex wrench, knife, Phillips head screwdriver, flat head screwdriver, scissors and measuring tape are rotatably associated with the funeral service apparatus to be configurable between an extended configuration and a stored configuration. Moreover, the holy water containment vial, the committal sand containment vial and the pen are slidably associated with the funeral service apparatus to be configurable between an extended configuration and a stored configuration.

Funeral service apparatus

A layout versus schematic (LVS) comparison tool determines one-to-one equivalency between an integrated circuit schematic and an integrated circuit layout by performing operations to color a schematic graph of a parent cell to an equilibrium state. An operation is then performed to recolor nets connected to first and second child cells having the same device value within the parent cell, using a net coloring operation that recolors a first plurality of symmetric pins of the first child cell and recolors a second plurality of symmetric pins of the second child cell. Distinct device values are then generated for the first and second child cells by determining a first product of the colors of the recolored first plurality of symmetric pins and a second product of the colors of the recolored second plurality of symmetric pins. The operations to recolor the nets preferably include coloring a first pin of a child cell within a parent cell using a pin coloring operation that is a function of a device value of the child cell and a color of each of the pins of the child cell that are independently swappable with the first pin, but is independent of a color of a second pin of the child cell that is dependently swappable with the first pin.

Methods, apparatus and computer program products that perform layout versus schematic comparison of integrated circuits using advanced pin coloring operations

Layout versus schematic (LVS) comparison tools that use advanced symmetry resolution techniques

A layout versus schematic (LVS) comparison tool performs layout versus schematic comparison of integrated circuits having memory cells and non-memory cells therein. These operations are particularly useful when the integrated circuit layout includes one or more arrays of memory cells (i.e., bit cells) that are identified at a transistor level in the layout netlist. Such operations include scanning a layout netlist of the integrated circuit at the transistor level to identify a first device therein that has an identifiable characteristic associated with the plurality of memory cells relative to the plurality of non-memory cells. Upon detection of the identifiable characteristic, the layout netlist of a first memory cell containing the first device is traced in order to identify a first bit line and/or a first word line therein that is electrically coupled to the first memory cell. This tracing operation preferably comprises tracing a netlist path extending from the first device to a first bit line or a first word line electrically connected to the first memory cell. This netlist path may include a path defined by one or more nets and devices connected together and preferably connected between the first device and the first bit line (or first word line). The first bit line and/or first word line is then traced locally to identify a plurality of additional memory cells electrically coupled thereto along a column or row. Additional bit lines and words lines that are connected to these identified memory cells can also be traced in a similar manner to identify a plurality of rows and columns of memory cells in a memory array block.

Methods, apparatus and computer program products that perform layout versus schematic comparison of integrated circuit memory devices using bit cell detection and depth first searching techniques

Methods, apparatus and computer program products that perform layout versus schematic comparison of integrated circuits using advanced symmetry resolution techniques

Growing community of inventors

Mebane, NC, United States of America

Jonathan Calvin White