Baysand Inc.

Altera Corporation

Easic Corporation

Jonathan C Park

Yin Hao Liew

Salah M Werfelli

Kok Seong Lee

Herman Henry Schmit

Steven Perry

Richard Louis Price

Gregor Nixon

Andrew Hall

Soon Chieh Lim

Alasdair Scott

Kok Siong Tee

Chris Dettmar

Larry Kong

Yau Kok Lai

Lingli Wang

WeiZhi Kang

Yit Ping Kok

Teck Siong Ong

Wan Tat Hooi

Jeremy Jia Jian Lee

Adam J Wright

Adam E Levinthal

Richard C Saito

Ronnie V Vasishta

Shu Ern Perng Mark

Wai Leng Chek

Eugen Chen

Evgueni Ratchev

Embodiments of the invention relate to a configurable register file for inclusion in ASIC and other integrated circuit designs such as those based on metal configurable standard cell (MCSC) technology. According to certain general aspects, configurable register files provided by the present embodiments improve area, power and routing efficiencies and flexibility over conventional approaches such as hard memory macros and RTL designs. In embodiments, a configurable register file is implemented as a soft macro constructed from metal configurable standard cell (MCSC) base cells. According to certain aspects, unlike a hard memory macro, width and depth are not fixed and can be configured or programmed to any desired dimension or configuration. In some embodiments, a bit array of a configurable register file is comprised of register file bit cells. In other embodiments, a bit array of a configurable register file is comprised of ROM bit cells. In these and other embodiments, a configurable register file is constructed with a bit-line sharing approach that improves the routing and logic resource usage as compared to RTL based memory.

Metal configurable register file

Embodiments of the invention relate to a metal configurable hybrid memory for use in integrated circuit designs for implementation in structured ASIC or similar platforms utilizing a base cell or standard cell. In accordance with certain aspects, a hybrid memory according to embodiments of the invention utilizes a fixed custom memory core and a customizable peripheral set of base cells. In accordance with these and further aspects, the hybrid memory can be specified using a macro, in which certain memory features (e.g. ECC, etc.) are implemented using the customizable peripheral set of base cells, and which may be selected or omitted from the design by the user. This enables the overall logic use for the memory to be optimized for a user's particular design. Unused logic in the customizable peripheral set of base cells can thus be freed for top-level logic use, thereby optimizing the design according to a user's functional and dimensional requirements and minimizing unnecessary waste of silicon area and power.

Metal configurable hybrid memory

Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. In other aspects, ESD circuitry is provided at corners of the IC layout and optionally within selected I/O slots. Decap circuitry is provided at an outer edge of the IC layout and is scalable in order to meet different requirements.

Flexible, space-efficient I/O circuitry for integrated circuits

Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD protection circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from power supply requirements of signal I/O buffers of another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. Customization circuitry also provides for flexible pad options, whereby the IC pads may be configured for different packaging technology, for example, for wire bonding for flip-chip bonding, or for other types of bonding.

An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.

Gate array architecture with multiple programmable regions

Systems and methods are disclosed for forming a custom integrated circuit (IC) with a first fixed (non-programmable) region on a wafer with non-customizable mask layers, wherein the first fixed region includes multiplicities of transistors and a first interconnect layer and a second interconnect layer above the first interconnect layer which form base cells; and a programmable region above the first fixed region with customizable mask layers, wherein at least one mask layer in the programmable region is coupled to the second interconnect layer which provides electrical access to all transistor nodes of the base cells and wherein the programmable region comprises a third interconnect layer coupled to the customizable mask layers to customize the IC. A second fixed region may be formed above the programmable region to provide multiple fixed regions and reduce the number of required masks in customizing the custom IC.

A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.

Programmable vias for structured ASICs

A user logic design for a mask-programmable logic device ('MPLD') may be designed on a comparable or compatible user-programmable logic device ('UPLD') and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD&#x2014;i.e., differences between the devices&#x2014;are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.

Method for programming a mask-programmable logic device and device so programmed

A configurable logic array may include a multiplicity of logic components, which may contain customizable look-up tables, and layers of fixed metal segments all of which may be customizable using a single custom via layer. The integrated circuit containing the configurable logic array may also include a multiplicity of customizable register files, customizable RAM blocks; a ROM block with customizable contents; or test logic with customizable test options and configurations to separately test logic and the PLLs.

Single via structured IC device

A method for verifying library components and designs on a via customizable ASIC, which may include the process of adding capacitors to model possible via sites of a model of an un-customized portion of or a whole ASIC, and replacing the capacitors with resistors to model where custom vias have been placed on the ASIC to implement a desired component or design. Views of this model may then be generated to verify the functionality of the component or design, and component models for timing, function and via customization may then be generated for the component library.

Programmable via modeling

A mask-programmable logic device that implements a pre-existing circuit design and that includes programmable smart switches is provided. The smart switches are metal terminals that may be programmed to perform configuration-related logic functions of the pre-existing circuit design.

Switch methodology for mask-programmable logic devices

A method for creating a mask-programmed device from a preexisting design of a source device is provided. The method includes creating a netlist from a user defined circuit configuration file, configuring logic resources on the mask-programmed device produce basic logic elements, and generating a custom interconnect based on the netlist that interconnects the configured logic resources to produce the desired logic design.

Method of creating a mask-programmed logic device from a pre-existing circuit design

A mask-programmable logic device includes a 'dedicated' device-wide distribution network for device-wide signals such as clocks. Distribution networks for secondary clocks and similar signals, as well as for other high-fanout signals, are designed on a custom basis for each user configuration to be implemented by mask programming, using design techniques that are well known in application-specific integrated circuit design. This accomplishes, at the same time, elimination of the need to custom design the device-wide distribution network for each user configuration, preservation of the timing characteristics of a comparable conventional programmable logic device on which the user configuration may be based, reduction of die-size and power requirements as compared to the comparable conventional programmable logic device, and reduction of the average design time necessary to implement a given user configuration.

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San Jose, CA, United States of America

Jonathan C Park