Intel Corporation

Tektronix, Inc.

Other

Jonathan C Lueker

Mehrab Sedeh

Burt L Price

John A Hengeveld

Richard L Coulson

Jim Schlegel

Brad Needham

Dean Warren

Robert W Faber

Scott B Blum

Bradford H Needham

William E Berg

Mark Isenberger

Hitesh Windlass

John E Carlson

Kenneth B Oliver

Steven D Kassel

Raymond A Zandonatti

Phil W Martin

John B Rettig

Stanley P Kaveckis

Roy W Lewallen

James Schlegel

The write disturb that occurs in polymer memories may be reduced by writing back data after a read in a fashion which offsets any effect on the polarity of bits in bit lines associated with the addressed bit. For example, each time the data is written back, its polarity may be alternately changed. In another embodiment, the polarity may be randomly changed.

Reducing the effect of write disturbs in polymer memories

The effects of a self-erase phenomenon when accessing imprinted ferroelectric memory cells that have non-conductive electrode interfaces that reduce remnant polarization and decrease signal margin are eliminated. A self-erase control pulse asserted after an access pulse is utilized. The self-erase control pulse has a magnitude sufficient to offset a remnant charge on the non-conductive electrode interfaces after the removal of the access pulse.

Minimization of signal loss due to self-erase of imprinted data

Briefly, one or more memory access parameters used to access a memory cell are adjusted based on a sensed operating temperature. In one embodiment, a pulse width of an access voltage is increased as the operating temperature decreases below a threshold. In another embodiment, a drive voltage is decreased as the operating temperature increases.

Temperature adaptive ferro-electric memory access parameters

Briefly, voltages to write a memory cell are adjusted if the memory cell is determined to be imprinted. In one embodiment, a positive voltage not including zero is applied to one of a bit line and a word line and a negative voltage not including zero is applied to another of the bit line and the word line to write a specified logic state to an imprinted memory cell. Neighboring cells do not receive disturb voltages in excess of a disturb voltage threshold.

Polymer de-imprint circuit using negative voltage

A pipelined Universal Serial Bus (USB) parallel frame delineator and non-return to zero invert (NRZI) decoder is described. Using a three-stage pipeline and parallel data stream processing, a USB transceiver delineates received asynchronous frame boundaries within a USB peripheral NRZI data stream. Using asynchronous parallel data stream processing the USB transceiver concurrently decodes received NRZI encoded data.

Pipelined, universal serial bus parallel frame delineator and NRZI decoder

In order to recover phase information, data transmitted at a first frequency is over-sampled using a clock at a second frequency, n times per bit time to obtain n samples. The n samples are used to detect the transitions between two logic levels in said transmitted data which are stored in groups of m sets of said n edge results which are, in turn output at a clock frequency which is the second frequency divided by m, for further processing.

Data recovery method and apparatus

A concurrent asynchronous USB 2.0 data stream destuffer and separator with variable-width bit-wise memory controller is described. A parallel stream bit destuffer module identifies in parallel one or more stuffed bits in a decoded data field of a received data stream using a six-bit sliding window. The stuffed bits are bits that were inserted into the received USB data stream by a transmitter to force data transitions in the received USB data stream. A data separator module separates the one or more stuffed bits from a plurality of valid data bits in the decoded data field. A memory module generates an incremental pointer value representative of the number of valid bits and writes the plurality of valid data bits from the decoded data field into a variable sized bit-wise memory structure.

Concurrent asynchronous USB data stream destuffer with variable width bit-wise memory controller

A method for dynamically balancing a serial data link is disclosed. The serial data link includes a first transmission line and a second transmission line. The method includes the steps of creating a DC offset voltage between the first and second transmission lines when the serial data link is in an idle state. When the serial data link is in use to carry data, the DC offset voltage between the first and second transmission lines is removed.

Dynamic line balancing scheme for providing inter-packet squelch

Incoming serial data which is received M bits at a time where M&equals;N, N&plus;1 or N&minus;1 and N is greater than 1 is synchronized to a local clock by receiving a first M bits of data, storing the first M bits, receiving M additional bits, storing the M additional bits, repetitively receiving and storing until at least a predetermined number R of bits have been stored, where R&equals;(M*X)&plus;1 where X is an integer greater than one. When this occurs, the first R bits are output and any remaining S bits in excess of R are stored and additional groups of M bits added, with the process continuing until all of a packet has been received. With this arrangement, the R bits may be output at a rate which is a fraction of the serial bit rate.

Data synchronization interface

A transparent proxy. In a computer system, a layered service provider intercepts a communications request from a client application in the native protocol of the communications request wherein the communications request requests communication with a remote server. The service provider bundles and passes the communications request to a predetermined port. A transparent proxy application listening on the predetermined port receives the communications request in the native protocol of the request and establishes the requested communication.

Transparent proxy server

In one embodiment of the invention, an access point for use in a powerline based network includes first physical layer circuitry to interface with a powerline and second physical layer circuitry to interface with an antenna. The access point also includes circuitry to interface between the first and second physical layer circuitry. The first and second physical layer circuitry and the circuitry to interface between the first and second physical layer circuitry allow an untethered electrical device to have data communication through the powerline with an electrical device tethered to the powerline. Under another embodiment of the invention, a powerline based network includes a powerline and an access point connected to the powerline and capable of wireless communication.

Wireless LAN segments with point coordination

A digital architecture for a pulse generator includes a triggerable voltage controlled oscillator (VCO) with two alternative sources of frequency control voltage, an internal DAC or a phase frequency comparison with an external timebase. In a top octave of operation, the output of the triggerable VCO is used to produce output pulses whose edge locations are then adjusted by small digital increments or 'slivers' and very small analog increments or 'verniers'. In lower octaves of operation, the contents of a pattern RAM serve to frequency divide the triggerable VCO output frequency by powers of two. The RAM contents are converted to a serial bit stream that imposes the coarse pulse width and period as an integral number of top octave periods, or quanta. The edge locations are then adjusted with slivers and verniers, as in the top octave. Automatic calibration facilities are included. This architecture provides controllable tolerances, permits accurate positioning of a trigger out signal relative to any pulse produced, allows the user to specify the trailing edge timing directly, and permits both pulse width and phase to be specified as a percentage of the overall period and automatically kept proportional when the frequency is varied. It also allows synchronized operation of different channels at rates related by powers-of-two, and permits the disabling of a channel at an operator determined voltage level. A means for determining, by the use of an external signal, when bursts of pulses synchronized to an external frequency source will begin, is also provided.

Digital pulse generator

A digital data generation system including a programmable dominance RS flip-flop has a random access memory that stores a user selected sequence of test data. A pattern formatting logic circuit receives the test data and produces, for each data period, a coarsely timed candidate pulse for identifying the leading edge of an output data pulse and a coarsely timed candidate pulse for identifying the trailing edge of the output data pulse. A precision delay circuit finely tunes the timing of the candidate pulses. The finely tuned pulses are applied to an RS flip-flop circuit which can be programmed for set or reset dominance, thereby preventing an indeterminate state when a logic '1' is applied to both the set and the reset input. In the system, the flip-flop is programmed so that the most recent of the lead pulse or the trail pulse prevails.

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Portland, OR, United States of America

Jonathan C Lueker