Xilinx, Inc.

Tsi Telsys, Inc.

Maxar Space LLC

Jonathan C Harris

Ian D Miller

Donald J Davis

Stephen G Edwards

Andreas Benno Kollegger

Toby D Bennett

James E Jensen

Christopher R S Schanck

Conor C Wu

Manuel Gonzalez-Rivero

David R Herdzik

Christopher Robert Sunderland Schanck

James W Bishop

Yung-Sheng Yu

Methods and structures are presented for implementing an automatic target recognition system as a convolutional neural network (CNN) in a satellite or other environment with constrained resources, such as limited memory capacity and limited processing capability. For example, this allows for the automatic target recognition to be implemented on a field programmable gate array (FPGA). Image data is split into subsets of contiguous pixels, with the subsets processed in parallel in a CNN of a corresponding processing node using quantized weight values that are determined in a training process that accounts for the constraints of the automatic target recognition system. The results of the automatic target recognition process is based on the combined output of the processing nodes.

Convolutional neural network (CNN) for automatic target recognition in a satellite

Determination of a convolutional neural network (CNN) for automatic target recognition in a resource constrained environment

A method of creating a multi-staged hardware implementation based upon a high level language (HLL) program can include generating a language independent model (LIM) from the HLL program, wherein the LIM specifies a plurality of state resources and determining a first and last access to each of the plurality of state resources. The method further can include identifying a plurality of processing stages from the LIM, wherein each processing stage is defined by the first and last access to one of the plurality of state resources. A stall point can be included within the LIM for each of the first accesses. The LIM can be translated into a scheduled hardware description specifying the multi-staged hardware implementation.

Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages

Generation of a hardware interface specification for a software procedure. In one embodiment, an HDL description is generated for a first memory, at least one first state machine, a second memory, at least one second state machine, and an activation signal. The first memory stores input data corresponding to a plurality of data values consumed by the software procedure. The first state machine receives the input data and stores the input data in the first memory, and at least one of the at least one first state machines receives a plurality of the data values. The second memory stores output data corresponding to at least one data value produced by the software procedure. The second state machine reads the output data from the second memory and sends the output data.

Generation of a hardware interface for a software procedure

A method of designing an integrated circuit using a general purpose programming language can include identifying a number of instances of each class allocated in a programmatic design implemented using the general purpose programming language and modeling the global memory of the programmatic design. A data flow between the modeled global memory and instructions of the programmatic design which access object fields can be determined and access to the modeled global memory can be scheduled. The programmatic design can be translated into a hardware description of the integrated circuit using the modeled global memory, the data flow, and the scheduled memory access.

Method of transforming software language constructs to functional hardware equivalents

A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model () and identifying data input to each component specified in the language independent model to determine a latency for each component (). The components of the language independent model can be annotated for generation of control signals such that each component is activated when both control and valid data arrive at the component (). Each component also can be annotated with an output latency derived from a latency of a control signal for the component and a latency determined from execution of the component itself ().

Scheduling hardware generated by high level language compilation to preserve functionality of source code design implementations

A method of processing a program written in a general purpose programming language to determine a hardware representation of the program can include generating a language independent model of the program written in a general purpose programming language () and identifying a loop construct within the language independent model (). A determination can be made as to whether the loop construct is bounded (). If so, a loop processing technique can be selected for unrolling the loop construct according to stored user preferences). The loop construct can be replicated in the language independent model as specified by the selected loop processing technique ().

Determining hardware generated by high level language compilation through loop optimizations

A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model (, and). The language independent model can be scheduled such that each component is activated when both control and valid data arrive at the component (). An interface structure specifying a hardware interface through which devices external to the language independent model interact with a physical implementation of the language independent model can be defined and included in the language independent model ().

Generating hardware interfaces for designs specified in a high level language

A method of designing an integrated circuit using a general purpose programming language can include identifying () a number of instances of each class allocated in a programmatic design implemented using the general purpose programming language and modeling () the global memory of the programmatic design. A data flow between the modeled global memory and instructions of the programmatic design which access object fields can be determined () and access to the modeled global memory can be scheduled (). The programmatic design can be translated () into a hardware description of the integrated circuit using the modeled global memory, the data flow, and the scheduled memory access.

The compilation of a high-level software-based description of an algorithm into efficient digital hardware implementation(s) is addressed. This is done through the definition of new semantics for software constructs with respect to hardware implementations. This approach allows a designer to work at a high level of abstraction, while the semantic model can be used to infer the resulting hardware implementation. These semantics are interpreted through the use of a compilation tool that analyzes the software description to generate a control and data flow graph. This graph is then the intermediate format used for optimizations, transformations and annotations. The resulting graph is then translated to either a register transfer level or a netlist-level description of the hardware implementation.

Means and method for compiling high level software languages into algorithmically equivalent hardware representations

A system and method for sending and receiving data with a reliable communication protocol. The system includes a computer at a node having a backplane, a CPU board plugged into the backplane, software instructions for the CPU, and a special network board plugged into the backplane. The CPU board, software, and network card act to implement the TCP/IP protocol suite. The network card or board includes an interface to receive data packets from the physical layer, and circuitry to verify the TCP checksum before de-encapsulation and routing of the TCP segment by the network layer software. It also includes circuitry to automatically prepare the acknowledgement signal to be sent by the receiving computer to the sending computer. It additionally includes circuitry to calculate the error detecting code on outgoing signals from the sending computer to the receiving computer.

System for transmitting and receiving data within a reliable communications protocol by concurrently processing portions of the protocol suite

A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities, and hardware functionalities. Further controlling and executing the hardware objects via high level software constructs and managing the reconfigurable resources, such that the reconfigurable resources are optimized for the tasks currently executing.

System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects

Apparatus and method for constructing data for transmission within a

A programmable circuit assembly and methods for high bandwidth data processing. The assembly includes an array of in-circuit programmable logic packages interconnected with an array of memory packages, allowing for elastic buffering of data in a variety of directions. Each programmable package includes package leads, a memory, and output drivers. Each output driver is connected to a respective package lead, which is configured to generate a logic function defined by programming data stored in the memory. A method includes storing programming data for operating the assembly to send signals on different paths between a programmable package and a memory package.

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Ellicott City, MD, United States of America

Jonathan C Harris