Unity Semiconductor Corporation

Lightwave Microsystems Corporation

Amprius, Inc.

Amprius Technologies, Inc.

Jonathan Bornstein

David Hansen

Robin W Cheung

Darrell Rinerson

Constantin Ionel Stefan

Weijie Wang

Song Han

Zuqin Liu

Travis Byonghyop Oh

Steven W Longcor

Lawrence Schloss

Fan Zhong

Rene Meyer

Pamela Shiell Trammel

David Menche

Travis Byonghyop

Daniel Seo

Provided herein are nanostructures for lithium ion battery electrodes and methods of fabrication. In some embodiments, a nanostructure template coated with a silicon-based coating is provided. The silicon coating may include a non-conformal, more porous silicon-rich SiElayer and a conformal, denser SiElayer on the non-conformal, more porous layer. In some embodiments, two different deposition processes are used: a PECVD layer to deposit the non-conformal, silicon-rich SiElayer and a thermal CVD process to deposit the conformal layer. The silicon-rich SiEmaterial prevents silicon crystalline domain growth, limits macroscopic swelling, increases lithium diffusion rate and enhances significantly battery life during lithium ion battery cycle of charge and discharge.

Compositionally modified silicon coatings for use in a lithium ion battery anode

Provided herein are nanostructures for lithium ion battery electrodes and methods of fabrication. In some embodiments, a nanostructure template coated with a silicon coating is provided. The silicon coating may include a non-conformal, more porous layer and a conformal, denser layer on the non-conformal, more porous layer. In some embodiments, two different deposition processes, e.g., a PECVD layer to deposit the non-conformal layer and a thermal CVD process to deposit the conformal layer, are used. Anodes including the nanostructures have longer cycle lifetimes than anodes made using either a PECVD or thermal CVD method alone.

Structurally controlled deposition of silicon onto nanowires

Conductive oxide electrodes are described, including a bi-layer barrier structure electrically coupled with an adhesion layer, and an electrode layer, wherein the bi-layer barrier structure includes a first barrier layer electrically coupled with the adhesion layer, and a second barrier layer electrically coupled with the first barrier layer and to the electrode layer. The conductive oxide electrodes and their associated layers can be fabricated BEOL above a substrate that includes active circuitry fabricated FEOL and electrically coupled with the conductive oxide electrodes through an interconnect structure that can also be fabricated FEOL. The conductive oxide electrodes can be used to electrically couple a plurality of non-volatile re-writeable memory cells with conductive array lines in a two-terminal cross-point memory array fabricated BEOL over the substrate and its active circuitry, the active circuitry configured to perform data operations on the memory array.

Conductive oxide electrodes

Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnO, LaSrCoO, LaNiO, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

Memory device using ion implant isolated conductive metal oxide

A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

Continuous plane of thin-film materials for a two-terminal cross-point memory

Memory cell formation using ion implant isolated conductive metal oxide

Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.

Method of making a planar electrode

Multi-step selective etching. Etching an unmasked region associated with each layer of a plurality of layers, the plurality of layers comprising a stack, wherein the unmasked region of each of the plurality of layers is etched while exposed to a temperature, a pressure, a vacuum, using a plurality of etchants, wherein at least one of the plurality of etchants comprises an inert gas and oxygen, wherein the etchant oxidizes the at least one layer that can be oxidized such that the etching stops, the plurality of etchants leaving substantially unaffected a masked region associated with each layer of the plurality of layers, wherein two or more of the plurality of layers comprises a memory stack, and preventing corrosion of at least one of the plurality of layers comprising a conductive metal oxide by supplying oxygen to the stack after etching the unmasked region without breaking the vacuum.

Multi-step selective etching for cross-point memory

A method for making a resistive heater for a planar lightwave circuit. The method includes the step of depositing a resistive layer on a top clad of a planar lightwave circuit. An interconnect layer is subsequently deposited over the resistive layer. The resistive layer can be tungsten and the interconnect layer can be aluminum. The interconnect layer is then etched to define a heater interconnect, wherein the heater interconnect is disposed over the resistive layer and has a first width. The heater interconnect is then masked, and the resistive layer is etched to define a resistive heater. The resistive heater is disposed beneath the heater interconnect and has a second width larger than the first width. The heater interconnect is defined to include a heater conduct region between a first contact pad and a second contact pad such that a current between the first contact pad and the second contact pad is conducted through the resistive heater, thereby generating heat which is conducted into the top clad of the planar lightwave circuit. The difference between the first width of the heater interconnect and the larger second width of the underlying resistive heater is determined to decrease an alignment sensitivity of a lithography process for masking the heater interconnect. A dry etch process can be used to etch the aluminum interconnect layer and/or the tungsten resistive layer. The dry etch process can be a reactive ion etching process. A wet etch process can be used to etch the aluminum interconnect layer, wherein the wet etch process does not attack the tungsten.

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Cupertino, CA, United States of America

Jonathan Bornstein