Intel Corporation

Jonathan B Sweedler

Harshvardhan P Sharangpani

Luke E Girard

Dror Avnon

A method and apparatus for executing floating-point instruction pairs in a pipelined manner in which exceptions are predicted during an execution stage. In response to a possible exception, the execution pipeline can stall the pipeline. The floating-point pipeline and the integer pipelines are stalled in an execution stage and a decoding stage, respectively. Once stalled, the floating-point microinstructions are executed, the state of the machine is updated and then any exceptions are reported.

Method and apparatus for executing floating point (FP) instruction pairs

A data register file system is provided in a microprocessor having a pipelined execution unit that employs the data register file to store operands and results of its instruction executions. The data register file system includes a plurality of data registers, each of which stores one of the operands and results. A pointer table has a plurality of pointer registers, each storing an address of one of the data registers. A first address generation logic is coupled to the pointer table and the pipelined execution unit for generating a first set of pointer table addresses to access a first group of the pointer registers for the addresses of a first group of the data registers which are required by the execution of a first floating point instruction. The first address generation logic services the first floating point instruction A second address generation logic is coupled to the pointer table and the pipelined execution unit for generating a second set of pointer table addresses to access a second group of the pointer registers for the addresses of a second group of the data registers which are required by the execution of a second instruction. The second address generation logic is provided specifically to facilitate the issue and execution of the second floating point instruction in parallel with the first floating point instruction The second instruction is an exchange instruction that requires an exchange of contents stored in the second group of data registers. A circuit is coupled to the pointer table and the data registers for coupling the addresses of the first group of the data registers to the data registers for accessing the first group of the data registers. A read circuit is coupled to the pointer table for reading the addresses of the second group of the data registers. An exchange circuit is coupled to the read circuit for exchanging the addresses read from the second group of the pointer registers and writing the addresses exchanged back to the second group of the pointer registers. The second instruction is issued and executed in parallel with the first instruction. A method of executing the exchange instruction in parallel with other instructions in the data register file system is also described.

Method and apparauts for parallel exchange operation in a pipelined

A hardware logic arrangement for subtraction using a 3:2 carry-save-adder (CSA) for use with high speed floating point computation circuits. Three operands to be combined are routed to the three inputs of the CSA via separate multiplexors (MUXs) and appropriate inverting logic. Output sum and carry vectors are routed via further MUXs to separate latch storage registers. Subtraction executed as addition of the inverse of an operand is implemented by routing a constant '1' to the MUX steering the output carry vector to its associated latch.

Methods and apparatus for subtraction with 3:2 carry-save adders

A safe instruction recognition method and apparatus for use in a pipelined floating-point processor is described. It is based on the examination of the exponents of each operand. A simple symmetric test, applicable to each exponent, is disclosed using the same fixed upper and lower limits. A parallel safe instruction recognition network is described that allows the simultaneous testing of both operand exponent lower and upper limits. All operands declared safe by this method ensure against floating-point processor overflow and underflow exceptions for add, subtract, multiply and divide operations.

Floating point safe instruction recognition method

Floating point safe instruction recognition apparatus

Apparatus for converting to a single precision or double precision number an extended precision floating point number comprised of a sign field, an exponent field and a mantissa field. A sticky generation logic connected to the mantissa bus calculates rounding bits for single and double precision and places the rounding information at a sticky output. Overflow and underflow detection logic connected to the exponent bus detects exponent overflow and underflow and generates an overflow output signal. Rounding and conversion control logic connected to the sticky output utilizes the type of conversion that has been specified and the rounding information at the sticky output for producing conversion controls at a control output and a conversion type signal output. A positional incrementer connected to the exponent bus, to the mantissa bus, and to the rounding and conversion control logic places on an incrementer output, the incremented number in response to the conversion type signal output of the rounding and conversion control logic. A conversion mux is connected to the exponent bus, to the mantissa bus, to the output of the positional incrementer and to the control output of the rounding and conversion control logic. In response to the control output of the rounding and conversion control logic means, the conversion mux places either the exponent bus and the mantissa bus, or the output of the positional incrementer means on a conversion output of the conversion mux.

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Sunnyvale, CA, United States of America

Jonathan B Sweedler