Finisar Corporation

Ii-vi Delaware, Inc.

Jonathan Ashbrook

Naresh Shanbhag

Brian R Carey

Hyeon Min Bae

Andrew Carl Singer

David Allouche

Lionel Li

Michael Chu

Nicholas F Jungels

Richard D Davis

Theron Jones

Anita Chan

Krzysztof Szczerba

Robert J Drost

Heyon Min Bae

Steve Troyer

Andrew Zocher

An optoelectronic assembly includes a printed circuit board (PCB), an integrated circuit (IC) substrate operably mounted on the PCB, the IC substrate comprising at least one of active elements and passive elements, a vertical-cavity surface-emitting laser (VCSEL) operably mounted on a first surface of the IC substrate, an optical detector operably mounted adjacent to the VCSEL on the first surface of the IC substrate, and a molding compound formed on the IC substrate encapsulating a plurality of sides of the VCSEL and a plurality of sides of the optical detector, in which at least one electrical communication path between the optical detector and the VCSEL is confined within the IC substrate.

Optoelectronic assembly

Laser drivers and methods are disclosed including a pulse input for receiving one or more logical pulse control signals, a delay circuit, a main pulse output, and a precharge pulse output for efficiently driving a laser with reduced time delay to desired optical output and reduced power consumption during between optical outputs.

Pre-charge modulation of a laser array for 3D imaging applications

An optoelectronic assembly is disclosed. The disclosed assembly includes one or more lasers formed on a first substrate, and a programmable driver circuit formed on a second substrate configured as an integrated circuit. The first and second substrates are mounted on a third substrate in a stacked arrangement.

An example embodiment includes a LCOS IC. The LCOS IC includes multiple pixels, a column driver, and multiple conductive lines. The pixels are arranged in a pixel array. The column driver is configured to supply multiple signals to a column of pixels included in the pixel array. Each of the conductive lines couples the column driver to a subset of pixels in the column of pixels. The conductive lines are configured such that two or more of the signals can be supplied to two or more of the subsets of pixels with some overlapping duration.

Pipelined pixel applications in liquid crystal on silicon chip

An example embodiment includes a liquid crystal on silicon (LCOS) system. The LCOS system includes multiple pixels, a pixel voltage supply source (voltage source), an external buffer, and a local buffer. The voltage source is configured to supply an analog ramp to the pixels. The external buffer is configured to buffer the voltage source from the pixels. The local buffer is configured to buffer the external buffer from a subset of pixels of the plurality of pixels.

Local buffers in a liquid crystal on silicon chip

An example embodiment includes a continuity testing method of a pixel in a liquid crystal on silicon integrated circuit. The method includes writing a first voltage to a pixel. The pixel is isolated and a wire that is selectively coupled to the pixel is discharged. The method also includes enabling a sensing amplifier configured to sense voltage on the wire. The pixel is electrically coupled to the wire and a resultant voltage on the wire is sensed.

Pixel test in a liquid crystal on silicon chip

A system and method is disclosed for controlling signal conditioning parameters and a sampling parameter controlling conversion of a received signal to digital sampled values prior to decoding. The sampled values are decoded according to a comparison with expected values calculated according to a model of a transmission channel. The model is also updated from time to time by comparing the expected values with actual sampled values. Variation of the expected values over time is calculated. One or more of the signal conditioning parameters and the sampling parameter are adjusted according to a numerical minimization method such that the system BER is reduced.

Tuning system and method using a simulated bit error rate for use in an electronic dispersion compensator

A peak detector circuit that responds rapidly to power transients, and yet is able to avoid interpreting data fluctuations as power transients by generating dual peak signals from an amplifier's differential output signal, where the dual peak signals have data ripple components that tend to cancel one another. The system and methods permit the peak detectors to be much more responsive to power transients by expanding their bandwidth (shortening the time constants) to the point that low frequency data components affect the individual peak detector signals, but the effects are cancelled out when the individual components are added together. The peak detector described herein may be used in an AGC system to provide ripple-free gain control signals, while rapidly following any power transients in transmitted signals.

Peak detector with active ripple suppression

Methods and systems are provided for an improved phase detector utilizing analog-to-digital converter (ADC) components. In an embodiment, the method includes from an ADC having a sampling clock signal that determines sampling instants, obtaining a first comparison value between an analog signal and a first threshold voltage at a first sampling instant, and obtaining a second comparison value between the analog signal and a second threshold voltage at a second sampling instant. The method further includes, from a supplemental circuit, obtaining a third comparison value between the analog signal and a third threshold voltage at a third sampling instant between the first and second sampling instants. The method further includes processing the first, second, and third comparison values to determine a phase relationship between the analog signal and the sampling clock.

Phase detector utilizing analog-to-digital converter components

A variable gain amplifier and offset cancellation loop circuit and methods for tracking and correcting DC offset errors that may vary in accordance with the gain of the variable gain amplifier. The circuit is designed to provide tracking of rapid changes in the offset error while maintaining a desired overall frequency response of the combined variable gain amplifier and offset loop. The offset loop cancellation circuit has a wide enough bandwidth to allow the offset cancellation loop to track rapid changes in offset errors that result from rapid changes to the amplifier's gain setting. A control circuit is provided to prevent the large offset cancellation loop bandwidth from having a detrimental effect on the amplifier's overall bandwidth when the amplifier is set to high levels of forward gain by adjusting the offset cancellation loop gain as the forward gain of the amplifier is altered.

Variable gain amplifier having variable gain DC offset loop

An electronic amplifier circuit that provides improved gain control linearity characteristics resulting from having a controllable field effect transistor (FET) acting as a degeneration resistance (degeneration resistance FET) and a controllable load resistance FET. The overall gain function of the amplifier exhibits improved linearity in part due to the presence of the load FET, which tends to cancel the nonlinear behavior emanating from the degeneration FET. The circuit also includes a control circuit for generating non-linear control signals that are responsive to process characteristics of the FETs, such that the degeneration resistance FET and load resistance FETs may be controlled more consistently and independently from process variations.

Growing community of inventors

Homer, IL, United States of America

Jonathan Ashbrook