Lsi Logic Corporation

Broadcom Corporation

Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Jonathan Alois Schmitt

Myron Buer

Laurentiu Vasiliu

Roger L Roisen

Roy Milton Carlson

Timothy V Statz

Joseph Eugene Glenn

Owen Hynes

Yong Lu

Todd A Randazzo

Douglas D Smith

Kenneth G Richardson

Iain Ross Mactaggart

Paul D Torgerson

Matthew Russell

Kenneth Stanley Szajda

Luong Hung

Jermyn Tseng

Gary Hom

Timothy McGonagle

Carol C Anderson

Steve Wurzer

Carol F Gillies

Eric W Eklund

A non-volatile memory cell, having an antifuse for storing data, is disclosed for use in a non-volatile data storage device. The non-volatile memory cell includes multiple redundant signal pathways to provide redundant access to the antifuse. During operation, the non-volatile memory cell can access the antifuse using a first signal pathway from among the multiple redundant signal pathways. However, when the first signal pathway is inoperable, the non-volatile memory cell is able to access the antifuse using a second signal pathway from among the multiple redundant signal pathways. The non-volatile memory cell is fabricated using a continuous region of one or more diffusion layers to allow efficient connection to other non-volatile memory cells to form an array of memory cells for the non-volatile data storage device.

Non-volatile memory cell having multiple signal pathways to provide access to an antifuse of the memory cell

A differential bit cell includes two memory elements that are configured to have different states. Each of the two memory elements is connected to a respective switching element. Each of these switching elements may have process variances, which may result in a degradation of read and/or write margins. To mitigate the effect of such variances, another switching element is coupled to the two memory elements and their respective switching elements in a manner that couples the aforementioned switching elements in a parallel fashion. In this way, the mismatch effects between the switching elements can be negated during read operations. During programming operations, such a configuration allows for the programming of both memory elements to different states with a single current pulse and also reduces the effective resistance of the programming path.

Differential bit cell

A bitcell may include an insulating region, a first doping proximate to the insulating region, and a second doping surrounding the first doping. The second doping can be characterized by a higher gate voltage breakdown than the first doping. Also, the bitcell may include a gate terminal, and the bitcell may be configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating region between the gate terminal and the first doping.

Method and system for split threshold voltage programmable bitcells

A programmable memory cell including a thick oxide spacer transistor, a programmable thin oxide anti-fuse disposed adjacent to the thick oxide spacer transistor, and first and second thick oxide access transistors. The thick oxide spacer transistor and first and second thick oxide access transistors can include an oxide layer that is thicker than an oxide layer of the programmable thin oxide anti-fuse. The programmable thin oxide anti-fuse and the thick oxide spacer transistor can be natively doped. The first and second thick oxide access transistors can be doped so as to have standard threshold voltage characteristics.

One-time programmable memory cell

A bitcell can include an insulating area, a first doping, a second doping, and a gate terminal for the insulating area. The second doping can be proximate to the first doping and proximate to the insulating area. The second doping can be characterized by a lower threshold voltage than the first doping. The bitcell can be configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating area between the gate terminal and the first doping.

A memory device includes an antifuse. The antifuse is configured to program a bit cell of the memory device. The antifuse is configured with a PMOS device.

A delay locked loop generates a voltage on a common node as a function of a phase difference between a reference input and a feedback input. A first voltage-controlled delay line coupled between the reference input and the feedback input and has a first delay, which is controlled by the voltage on the common node. A second voltage-controlled delay line is selectively coupled in series with the first delay line, between the reference input and the feedback input, as a function of a test control input. The second delay line has a second delay, which is controlled by the voltage on the common node.

Delay locked loop having internal test path

Methods and systems for split threshold voltage programmable bitcells are disclosed and may include selectively programming bitcells in a memory device by applying a high voltage to a gate terminal of the bitcells, where the programming burns a conductive hole in an oxide layer above a higher threshold voltage layer in a memory device. The bitcells may comprise an oxide layer and a doped channel, which may comprise a plurality of different threshold voltage layers. The plurality of different threshold voltage layers may comprise at least one layer with a higher threshold voltage and at least one layer with a lower threshold voltage. The oxide may comprise a gate oxide. The bitcell may comprise an anti-fuse device. The layer with a higher threshold voltage may be separated from an output terminal of the bitcell by the at least one layer with a lower threshold voltage.

A one-time programmable memory. The one-time programmable memory has an antifuse and a read circuit configured to read the antifuse. An isolation transistor couples the antifuse to the read circuit. The read circuit and the isolation transistor have different power domains.

One time programmable memory

Herein described is a method of implementing one or more native NMOS antifuses in an integrated circuit. Also described is a method for programming one or more native NMOS antifuses used within a memory device. The method further comprises verifying one or more states of the one or more native NMOS antifuses after the programming has been performed. In a representative embodiment, the one or more native NMOS antifuses are implemented by blocking the implantation of a dopant into a substrate of an integrated circuit. In a representative embodiment, an integrated circuit incorporates the use of one or more native NMOS antifuses. In a representative embodiment, the integrated circuit comprises a memory device, such as a one time programmable memory.

Memory device using antifuses

A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a '0' or a '1' depending on the side having the programmed fuse.

Quad SRAM based one time programmable memory

A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as to result in the improved IV characteristics. The programmable antifuse is proximate to one side of the spacer transistor, while the access transistor is proximate to an opposite side of the spacer transistor. The source region of the access transistor is coupled to ground, and the drain region of the access transistor also serves as the source region of the spacer transistor. The access transistor is coupled to a row line, while the spacer transistor and the programmable antifuse are coupled to a column line. The rupture site is formed during programming by applying a programming voltage to the programmable antifuse.

A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across a trigger point adjustment element. In one embodiment, the trigger point adjustment element can be a diode. The trigger voltage of the programmable memory cell is raised closer to a supply voltage when current passes through the trigger point adjustment element during a write operation. The programmable memory cell can comprise a pair of cross-coupled inverters, and first and second programmable antifuses that can be coupled to each inverter in the pair of cross-coupled inverters. Since the trigger voltage of the programmable memory cell is raised closer to the supply voltage, a programmed antifuse can easily reach below the trigger voltage and result in a successful write operation even when the supply voltage is a low voltage.

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Eden Prairie, MN, United States of America

Jonathan Alois Schmitt