Unisys Corporation

Toshiba America Electronic Components, Inc.

Jonathan A Levi

Luverne Ray Peterson

Laszlo V Gal

Richard J Petschauer

Roy R Shanks

Cevat Kumbasar

Roger Mar

David W Waite

Paul Abelovski

Steven S Wei

A generalized method for testing DACs (Digital to Analog Converters) and ADCs (Analog to Digital Converters), such as Sigma Delta (Successive Approximation), Pipeline or Flash ADCs. The DACs and ADCs are tested in pairs using a Digital Tester and on chip test circuitry. The DACs and ADCs may be tested at the highest clock frequency allowed in the specification, shortening test time. The test circuits required for this test scheme comprise cell logic two multiplexer cells and an internal Analog Test Bus. This scheme is extendable to the testing of many DACs and ADCs on the same IC. The number of DACs and ADCs need not be equal. Furthermore, the DACs may have more (or less) bits (addresses) than the ADCs. An ADC may be tested with more than one DAC or vice versa to determine which cell is at fault if a test fails.

Digital BIST test scheme for ADC/DAC circuits

An integrated circuit test wafer quickly detects A-C defects in any process by which the wafer is fabricated. This test wafer includes a semiconductor substrate having a major surface, and a diagnostic circuit that is repeatedly integrated over most of the wafer's surface. Each diagnostic circuit includes: a) a plurality of ring oscillators which generate respective cyclic output signals; b) an addressing circuit that receives external input signals and in response selects an output signal from any particular ring oscillator of the plurality; c) a timing circuit that generates a timing signal with a certain time period; and, d) a counting circuit that counts the number of cycles that occur in the selected output signal during the time period and provides that number as an output. By comparing the relative or absolute speeds of all of the ring oscillators, a ring oscillator with an A-C defect is detected; and, a defective ring oscillator can then be analyzed under an E-beam microscope to determine the defects cause. Preferably, the ring oscillators occupy at least 90% of the test wafers surface so that A-C defects are detected even when they are sparsely distributed on the test wafer.

Test wafer for diagnosing flaws in an integrated circuit fabrication

An improved standard cell logic chip, of the type which contains one to fifteen thousand standard logic cells that are disposed in rows on a substrate, and has cell interconnect channels of different widths between the rows, also includes fast change logic cells which are sparsely distributed in the rows of standard logic cells. Each fast change cell selectively performs any one of several logic functions. These fast change logic cells are formed from the same stacked conductive and insulative layers as the standard logic cells; however, in the fast change cells, all conductive and insulative layers which are below at least the mid level in the stack of layers have respective patterns which are identical in every fast change cell. Only the remaining conductive and insulative layers in the fast change cells have respective patterns which differ from one fast change cell to another, and they select the logical functions which the fast change cells perform.

Fast change standard cell digital logic chip

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Fallbrook, CA, United States of America

Jonathan A Levi