Arm Limited

Jonas Švedas

Fernando Garcia Redondo

Sahan Sajeewa Hiniduma Udugama Gamage

Andy Wangkun Chen

James Edward Myers

Parameshwarappa Anand Kumar Savanth

Rahul Mathur

Cyrille Nicolas Dray

Pranay Prabhat

Yannis Jallamion-Grive

Graham Peter Knight

Yann Sarrazin

Julien Vincent Poitrat

A method comprising, in response to a power-drop warning, beginning a checkpointing process comprising storing, to a non-volatile memory, execution state associated with data processing operations performed by data processing circuitry. The method also comprises maintaining, in the non-volatile memory, a checkpoint-progress indication to indicate which of multiple sections of the execution state have been stored as part of the checkpointing process.

Checkpoint-progress status

In response to a power-loss warning event occurring during data processing, a checkpointing process is performed to save a checkpoint of context data associated with the data processing to non-volatile data storage. In response to detection of a power recovery event occurring when the checkpointing process is still in progress, it is determined whether a checkpoint abort condition is satisfied, based at least on a checkpoint progress indication indicative of progress of the checkpointing process. If the checkpoint abort condition is unsatisfied, the checkpointing process can continue. If the checkpoint abort condition is satisfied, the checkpointing process is aborted to allow the data processing to resume.

Checkpointing

Briefly, embodiments, such as methods and/or systems for employing memory devices.

System, method and/device for managing memory devices

Briefly, embodiments of claimed subject matter relate to adjusting, such as extending, a clock signal to permit completion of a write operations to a first memory type and/or to permit completion of read operations from a second memory type, wherein the first memory type and the second memory type are dissimilar from each other. In certain embodiments, the first memory type may comprise a magnetic random-access memory (MRAM) cell array, and the second memory type may comprise a static random-access memory (SRAM) cell array.

Selective clock adjustment during read and/or write memory operations

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Cambridge, United Kingdom

Jonas Švedas