Infineon Technologies Ag

Jon Stanley Berry, Ii

Michael Maldei

Guenter Gerstmeier

Steven Michael Baker

Brian Cousineau

Jinhwan Lee

Malati Hedge

Jinwhan Lee

Wenchao Zheng

Malati Hegde

A system and method for distributing signals throughout an integrated circuit (IC). The system comprises a transmitter unit and a plurality of receiver units. The transmitter unit combines a plurality of signals into a serial signal stream and couples the serial signal stream to a conductor for distribution to a plurality of destinations in the IC. There is a receiver unit at each of the plurality of destinations and connected to the conductor. Each receiver unit extracts one of the plurality of signals from the serial signal stream received on the conductor. The transmitter unit comprises a multiplexer circuit and a counter circuit and time multiplexes the plurality of signals to form a serial signal stream, wherein a signal is selected for a time slot based on a count value of the counter circuit. The counter signal is also supplied to each receiver unit, which uses the counter signal to determine when to latch a signal from the serial signal stream.

Distribution of signals throughout a spine of an integrated circuit

A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

High density DRAM with reduced peripheral device area and method of manufacture

A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

Maskless middle-of-line liner deposition

A dynamic random access memory (DRAM) structure having a distance less than 0.14 &#x3bc;m between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The capacitor includes a semiconductor substrate that includes a plurality of insulation islands. An insulation layer is formed over the semiconductor substrate. Gate electrodes are formed on top of the insulation layer. An array of CD contact pads including a plurality of CD contacts are connected to the semiconductor substrate in a first predetermined number of locations. An array of CG contact pads including at least one CG contact connected to the gate electrodes such that each CG contact is connected to a respective gate electrode above a respective insulation island in a second predetermined number of locations.

Growing community of inventors

Raleigh, NC, United States of America

Jon Stanley Berry, Ii