Sun Microsystems, Inc.

Thinking Machines Corporation

Jon P Wade

Guy Lewis Steele, Jr

Steven K Heller

Daniel R Cassiday

W Daniel Hillis

Shaw-Wen Yang

Zahi S Abuhamdeh

Mahesh N Ganmukhi

David C Douglas

Monica C Wong-Chan

Robert C Zak, Jr

Jeffrey V Hill

Robert D Lordi

Margaret A St Pierre

Scott J Smith

Thomas F Knight, Jr

Bradley C Kuszmaul

Edward C Parish

David S Wells

William K Stewart

In brief summary, the invention provides a new message packet transfer system, which may be used in, for example, a multiprocessor computer system. The message packet transfer system comprises a plurality of switching nodes interconnected by communication links to define at least one cyclical packet transfer path having a predetermined diameter. The switching nodes may be connected to, for example, digital data processors and memory to form processing nodes in an multiprocessor computer system, and/or to other sources and destinations for digital data contained in the message packets. The switching nodes transfer message packets each from a respective one of the switching nodes as a respective source switching node to a respective one of the switching nodes as a respective destination switching node. At least one of the switching nodes has a plurality of buffers for buffering a corresponding plurality of message packets that it (that is, the at least one of the switching nodes) receives from another of said switching nodes during a message transfer operation, which ensures that deadlock does not occur during the message transfer operation.

System for performing deadlock free message transfer in cyclic multi-hop digital computer network using a number of buffers based on predetermined diameter

Methods and systems consistent with the present invention provide a family of networks ranging from 2 nodes to 16 nodes that can be partitioned in an unconstrained manner. That is, where the number of nodes in one of these networks is N, subnetwork can contain any number of nodes from 1 to N&minus;1 as long as the total number of nodes in both subnetworks equals N. Furthermore, each subnetwork can be partitioned repeatedly until reaching the atomic level (i.e., when the subnetwork contains a single node). In accordance with methods and systems consistent with the present invention, when a network is partitioned, each subnetwork has various desirable properties. For example, the maximum path length between any two nodes in each subnetwork nodes is 3, and each to subnetwork has a set of deadlock-free routings.

Recursive partitioning of networks

In accordance with methods and systems consistent with the present invention, an improved technique for reconfiguring networks is provided. By using this technique, a network administrator can reconfigure their network while it remains operational. As a result, users can continue to utilize the network during reconfiguration. Additionally, in accordance with methods and systems consistent with the present invention, a number of network topologies are provided that are designed to facilitate reconfiguration. When using one of these topologies, the network can be reconfigured with a minimal amount of recabling, thus reducing the amount of time required for reconfiguration.

Network reconfiguration

In accordance with methods and systems consistent with the present invention, a number of improved network topologies are provided that have been selected to improve network performance based on various performance characteristics. The topologies are also selected to facilitate network reconfiguration, including adding nodes and removing, nodes. As a result, the network topologies in accordance with methods and systems consistent with the present invention do not follow a rigid, predefined pattern; rather, these topologies have been selected for network performance purposes as well as reconfiguration purposes.

Network topologies

A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.

Massively parallel computer including auxiliary vector processor

System for performing deadlock free message transfer in cyclic multi-hop

A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.

A resistor circuit includes a resistance control circuit and at least one insulated gate field effect transistor. The resistance control circuit includes a control signal output element including a reference transistor for generating a resistance control signal in response to an internal control signal to maintain the reference transistor at a selected resistance value and a resistance value control element including a reference resistor for generating a circuit control signal for controlling the resistance value of the reference transistor in relation to the resistance value provided by the reference resistor. The field effect transistor is controlled by the resistance control signal to provide a resistance value which is a function of the resistance value of the reference transistor (and therefore of the reference resistor) and ratios of selected physical characteristics of the reference transistor.

Resistor circuit for integrated circuit chip using insulated field

A new driver circuit and receiver circuit for transmitting and receiving a differential signal pair. The driver circuit includes true and complement signal generating elements that generate a differential signal pair in tandem. Each of the true and complement signal generating elements includes a high-gain element and at least one low-gain element. The delay circuit is responsive to the true and complement data signal for iteratively controlling the high-gain element and low-gain element of each signal generating element to effect the generation of the differential signal pair, the delay circuit controlling the high-gain element with a delay relative to the low-gain element to thereby reduce ringing in the differential signal pair. The receiver circuit receives a differential receive signal pair, comprising true and complement receive signals having selected conditions over a pair of input lines and generates a true and complement data signal. The receiver circuit, during normal receiving operations, generates true and complement signals in response to the differential receive signal pair. During a test mode, the receiver circuit, in separate steps, compares the voltage levels of the true and complement receive signals to threshold voltages and generates an error signal if the selected true or complement receive signal does not have the proper relationship to the voltage level of the threshold voltage.

Differential driver/receiver circuit

A clock buffer circuit that generates a local clock signal in response to a system clock signal. The clock buffer circuit includes a buffer circuit for generating the local clock signal in response to an intermediate clock signal. A buffer control circuit generates the intermediate clock signal in response to the system clock signal and the local clock signal. The buffer control circuit provides a variable delay so that, with an additional delay provided by the buffer circuit, the local clock signal has a selected phase relationship in relation to the system clock signal.

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Cambridge, MA, United States of America

Jon P Wade