Altera Corporation

Jon Michael Harris

Boon Hong Oh

Vivek Gowri-Shankar

Integrated circuits with interpolating circuitry for deinterlacing video data are provided. Each frame of video data may include a field of pixels from every-other row of the frame. Edge detection circuitry may generate an edge map for the field. The edge map may be filtered to remove weak edges from the map. Cartesian Hough transformation circuitry may perform Cartesian Hough transforms on the filtered edge map to generate a Cartesian Hough space histogram. The Cartesian Hough space histogram may be filtered to remove bins having insufficient counts. Offset mask generation circuitry may generate an offset mask based on the Cartesian Hough space histogram. Interpolation circuitry may generate interpolated pixel values for missing rows of the field using pixels from the field and the offset mask. The interpolating circuitry may generate deinterlaced video data that is free from image artifacts along low-angle edges using the interpolated pixel values.

Hough transformation deinterlacing circuitry

A deinterlacing apparatus includes a buffer to receive a plurality of consecutive fields of an interlaced video and a field combination module coupled to the buffer to deinterlace the interlaced video in accordance with cadence of the interlaced video. The deinterlacing apparatus also includes a cadence detection module to detect the cadence by (1) causing each of the fields to be combined with its preceding field into a frame and with its subsequent field into another frame to obtain a plurality of combined frames, (2) determining a comb factor of each of the combined frames to obtain a sequence of comb factors of the combined frames, and (3) determining if the sequence of comb factors of the combined frames follows a pre-determined repeating pattern. A cadence detection method is also described.

Method and apparatus for performing robust cadence detection in a video deinterlacer

A method for interpolating an image field with image processing circuitry includes identifying, from a first row in the image field, a pixel to be interpolated. Edge direction vectors from the identified pixel and a plurality of neighboring pixels in a second row of the image field are determined. The edge direction vectors may then be combined to produce an interpolated pixel. The edge direction vectors may be combined such that the pixel is interpolated along each edge direction vector to obtain multiple interpolated pixel values. The pixel may be interpolated based on a weighted average of the interpolated pixel values.

Circuitry and techniques for image processing

A method of deinterlacing an interlaced video having a plurality of fields is described. The method includes detecting cadence of each pixel of each of the fields of the interlaced video. The interlaced video is then deinterlaced in accordance with the cadence, if any, of each of the pixels of each of the fields of the interlaced video. A pixel-based multi-cadence detection method is also described. Moreover, a pixel-based multi-cadence detection apparatus is also described.

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North Stoke, United Kingdom

Jon Michael Harris