Ovonyx Inc.

Bae Systems Information and Electronic Systems Integration Inc.

Other

Electronic Systems Integration Inc.

Bae Systems Information and Ovonyx, Inc

Jon Maimon

Tyler A Lowrey

Patrick K Klersy

John C Rodgers

Carl Schell

Stephen J Hudgens

Andrew T Pomerene

Ed Spall

David Sargent

Steve Hudgens

Jeff Fournier

Mike Hennessey

Wally Czubatyj

Guy Charles Wicker

Frederick T Brady

Murty S Polavarapu

A memory includes a programmable resistance array with high ratio of dynamic range to drift coefficient phase change memory devices.

Programmable resistance memory

A memory or switching device includes a mesa and a first electrode conforming to said mesa. The device also includes a second electrode and a phase-change or switching material disposed between said first and second electrodes. The phase-change or switching material is in electrical communication with the first and second electrodes at a first contact region and a second contact region respectively. Also described is a method for making a memory or switching device. The method includes providing a first insulator and configuring the first insulator to provide a mesa. A first conductive layer is provided conforming to the mesa. A phase-change or switching material is provided over a portion of the first conductive layer, and a second conductive layer is provided over the phase-change or switching material.

Memory device

A variable resistance material for memory applications. The material includes a base Ge&#x2014;Sb&#x2014;Te composition and further includes As-doping. The materials were included in variable resistance memory devices. Incorporation of As in the variable resistance composition led to a significant increase in the operational life of the device and, unexpectedly, did not reduce the programming speed of the device. In one embodiment, the composition includes at atomic concentration of Ge in the range from 7%-13%, an atomic concentration of Sb in the range from 50%-70%, an atomic concentration of Te in the range from 20%-30%, and an atomic concentration of As in the range from 2%-15%.

Arsenic-containing variable resistance materials

A programmable resistance memory element using a conductive sidewall layer as the bottom electrode. The programmable resistance memory material deposited over the top edge of the bottom electrode, in a slot-like opening of a dielectric material. A method of making the opening.

Programmable resistance memory element and method for making same

A method for making a tapered opening. The defined tapered opening is useful for the fabrication of programmable resistance memory elements. The programmable resistance memory material may be a chalcogenide.

Method for making tapered opening for programmable resistance memory element

Programmable resistance memory element

A method of making an electrically operated programmable resistance memory element. A sidewall spacer is used as a mask to form a raised portion of a conductive layer. A programmable resistance material is formed in electrical contact with the raised portion.

Method for making programmable resistance memory element

A method for manufacturing sidewall contacts for a chalcogenide memory device is disclosed. A first conductive layer is initially deposited on top of a first oxide layer. The first conductive layer is then patterned and etched using well-known processes. Next, a second oxide layer is deposited on top of the first conductive layer and the first oxide layer. An opening is then etched into at least the first oxide layer such that a portion of the first conductive layer is exposed within the opening. The exposed portion of the first conductive layer is then removed from the opening such that the first conductive layer is flush with an inner surface or sidewall of the opening. After depositing a chalcogenide layer on top of the second oxide layer, filling the opening with chalcogenide, a second conductive layer is deposited on top of the chalcogenide layer.

Method for manufacturing sidewall contacts for a chalcogenide memory device

A method of making an electrically operated programmable resistance memory element. A sidewall spacer is used as a mask to form raised portions on an edge of a conductive sidewall layer. The modified conductive sidewall layer is used as an electrode for the memory element.

A programmable resistance memory element using a conductive sidewall layer as the bottom electrode. The programmable resistance memory material deposited over the top edge of the bottom electrode in a slot-like opening formed in a dielectric material. A method of making the opening using a silylated photoresist.

Neutral conductivity ions, preferably germanium, are implanted through the oxide of a metal oxide semiconductor after isolation formation to provide a nearly constant threshold voltage for transistor operation independent of transistor channel width as device geometries are scaled down in size. The present invention sets forth a method for fabricating a metal oxide semiconductor (MOS) structure that controls threshold voltage V in the structure, the method including generating an isolation region of the semiconductor structure on a major surface of a silicon substrate, growing a thin oxide on the major surface of the semiconductor structure, implanting a large diameter neutral conductivity type ion into the major surface of the semiconductor structure through the thin oxide, annealing the semiconductor structure having the neutral conductivity ion implanted therein, and processing the semiconductor structure to create MOS devices having a near constant threshold voltage over a range of device channel widths.

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Manassas, VA, United States of America

Jon Maimon