Altera Corporation

Vlsi Technology, Inc.

Lsi Logic Corporation

Intel Corporation

Other

Jon M Long

Joel Martinez

Sergey Yuryevich Shumarayev

Peng T Li

Weiqi Ding

Louis H Liang

Michael J Steidl

Mike Peng Li

Yuming Tao

Anilkumar Raman Pannikkat

Rachel S Sidorovsky

Martin Langhammer

Bruce B Pedersen

Arifur Rahman

Mark R Schneider

Nagesh K Vodrahalli

John Pierre McCormick

Yuanlin Xie

Bidyut Kanti Sen

Richard G Smolen

Tien Duc Pham

Peng Li

Vincent Hool

Sadanand R Patil

Joseph W Foerstel

Adrian S Murphy

Thomas A Visel

Tarun Verma

Larry Anderson

V K Sahakian

A multichip package may include at least a package substrate, a main die mounted on the package substrate, a transceiver die mounted on the package substrate, and an optical engine die mounted on the package substrate. The main die may communicate with the transceiver die via a first high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die may communicate with the optical engine die via a second high-bandwidth interconnect bridge embedded in the package substrate. The transceiver die has physical-layer circuits that directly drive the optical engine. An optical cable can be connected directly to the optical engine of the multichip package.

Integrated circuit package with electro-optical interconnect circuitry

Systems and methods are provided to improve flexibility of optical signal transmission between integrated circuit devices, and more specifically data utilization circuits. More specifically, the integrated circuit devices may include a data utilization circuit communicatively coupled to a field programmable optical array (FPOA). In some embodiments, the FPOA may convert an electrical signal received from the data utilization to an optical signal, route the optical signal to an optical channel, and multiplex the optical signal with other optical signals routed to the optical channel. Additionally or alternatively, the FPOA may de-multiplex a multiplexed optical signal based on wavelength, route an optical signal included in the multiplexed optical signal to an electrical channel, convert the optical signal into an electrical signal, and output the electrical signal to the data utilization circuit via an electrical channel. In some embodiments, the FPOA may improve flexibility by performing such functions without reconfiguring the data utilization circuit.

Integrated circuit device with field programmable optical array

A system includes an encoding circuit, a line quality monitor circuit, and a controller circuit. The encoding circuit generates a first data signal indicating encoded data using a first forward error correction code. The line quality monitor circuit generates an indication of a line quality of a second data signal using an eye monitor circuit that monitors the second data signal. The controller circuit causes the encoding circuit to generate encoded data in the first data signal using a second forward error correction code in response to a change in the indication of the line quality of the second data signal.

Techniques for variable forward error correction

An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.

Apparatus for stacked electronic circuitry and associated methods

An integrated circuit (IC) package with a plurality of contact leads and a plurality of contact pads disposed on a surface of the IC package is disclosed. The contact pads may be used as test probes for testing the IC. Having a plurality of contact pads may create more test locations on the IC package. The size of the IC package may also be reduced by using contact pads instead of contact leads for testing. A socket body for the IC package is also disclosed. The socket body has a plurality of contactors extending outward from the socket body. The contactors may have different heights to contact each of the contact pads and contact leads on the IC package. The contactors may be adjustable to different heights. In some embodiments, a portion of the contactors may be compressed when and IC package is placed in the socket body.

IC package for pin counts less than test requirements

A method of fabricating an electronic assembly includes fabricating first and second interconnects. The first interconnect is adapted to interconnect a first die to a substrate. The second interconnect is adapted to interconnect the first die to a second die. The method further includes assembling the first die, the second die, and the substrate together such that the first die is disposed above the substrate, and the second die is disposed below the first die.

Electronic assembly apparatus and associated methods

Systems that provide integrated circuit device circuitry having an integrated optical-electronic interface for high-speed off-device communications are provided. An optical-electronic interface may be incorporated into an integrated circuit device, freeing up some or all of the electrical I/O pins of the integrated circuit device. Transceiver I/O channels may be provided on an integrated circuit device that can be switched between electrical and optical transceiver I/O channels.

Integrated optical-electronic interface in programmable integrated circuit device

Systems and methods for stacking a memory chip with respect to an integrated circuit (IC) chip are described. In the systems and methods, a plurality of like memory chips are stacked above one or more IC chip members of a family. The use of a plurality of like memory chips for the family may save costs and complications involved in designing, fabricating, and assembling memory chips of different sizes. The use of a plurality of the memory chips on a single IC chip can enable higher data transfer rates due to parallel data transmission.

Systems and methods for stacking a memory chip above an integrated circuit chip

The present invention is directed a novel method and apparatus for reducing crosstalk in a lead frame based electrical device package. One cause of the crosstalk in the lead frame package is the mutual inductance between adjacent lead fingers. A conductive sheet or mesh is introduced into the lead frame package such that one edge of the conductive sheet is below the die attach pad and electrically connected to the die and another edge is below the lead fingers and electrically connected to the ground lead of the package. Such arrangement significantly reduces the inductive coupling between adjacent lead fingers by coupling the lead fingers with the conductive sheet. The conductive sheet includes an array of through holes allowing the encapsulant material from the two sides of the sheet to flow smoothly together into one body.

Reduced inductance IC leaded package

A package-board co-design methodology preserves the signal integrity of high-speed signals passing from semiconductor packages to application PCBs. An optimal architecture of interconnects between package and PCB enhances the signal propagation, minimizes parasitic levels, and decreases electromagnetic interference from adjacent high frequency signals. The invention results in devices with superior signal quality and EMI shielding properties with enhanced capability for carrying data stream at multiple-gigabit per second bit-rates.

Ball grid array package-to-board interconnect co-design apparatus

An elongated bonding pad comprises two areas, a bonding area and an elongated probing area. The bonding area is located on the edge of an integrated circuit device for wire bonding. The elongated probing area is located on the inner area of the device. The long dimension of the elongated probing area is large enough for carrying a probing mark and the short dimension of the probing area is electrically and mechanically connected to the bonding area. Such elongated bonding pad can reduce the possibility of bonding wire open failures caused by wafer sort probing and increase the device's capacity of hosting more electrical components.

Elongated bonding pad for wire bonding and sort probing

The present invention includes a semiconductor package and a method of making the semiconductor package. The semiconductor package comprises an IC chip and a substrate, wherein part of the substrate routing such as substrate level trace routing is placed on the IC chip using post-passivation thick metal process at wafer level.

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Livermore, CA, United States of America

Jon M Long