Src Computers, Inc.

Arbor Company, Lllp

Cray Computer Corporation

Medallion Technology, LLC

Fg Src, LLC

Src Labs, LLC

Jon M Huppenthal

Lee A Burton

Paul A Leskar

Thomas R Seeman

D James Guzy

David E Caliga

Steven E Garcia

James A Harden, Jr

Timothy J Tewalt

Catherine A Herzog

Joseph E Jaramillo

Denis O Kellam

Candy L Saunders

A multi-processor computer architecture incorporating distributed multi-ported common memory modules wherein each of the memory modules comprises a control block functioning as a cross-bar router in conjunction with one or more associated memory banks or other data storage devices. Each memory module has multiple I/O ports and the ability to relay requests to other memory modules if the desired memory location is not found on the first module. A computer system in accordance with the invention may comprise memory module cards along with processor cards interconnected using a baseboard or backplane having a toroidal interconnect architecture between the cards.

Multi-processor computer architecture incorporating distributed multi-ported common memory modules

A reconfigurable processor module comprising hybrid stacked integrated circuit ('IC') die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array ('FPGA') die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.

Reconfigurable processor module comprising hybrid stacked integrated circuit die elements

Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search algorithms, information security, chemical and biological applications, filtering and the like as well as for systolic wavefront computations for fluid flow and structures analysis, bioinformatics etc. Some applications may also employ both the multi-dimensional pipeline and systolic wavefront methodologies disclosed.

Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions

A switch/network adapter port ('SNAP&#x2122;') in a dual in-line memory module ('DIMM') or Rambus&#x2122; in-line memory module (&#x201c;RIMM&#x201d;) format for clustered computers employing multi-adaptive processor (&#x201c;MAP&#xae;&#x201d;, both trademarks of SRC Computers, Inc.) elements for use with interleaved memory controllers. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format adapter port coupled to a reconfigurable processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (&#x201c;AGP&#x201d;) or system maintenance (&#x201c;SM&#x201d;) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (&#x201c;FPGA&#x201d;) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers

A switch/network adapter port ('SNAP') for clustered computers employing multi-adaptive processor ('MAP&#x2122;', a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (&#x201c;DIMM&#x201d;) or Rambus&#x2122; in-line memory module (&#x201c;RIMM&#x201d;) format to significantly enhance data transfer rates over that otherwise available through use of the standard peripheral component interconnect (&#x201c;PCI&#x201d;) bus. Particularly disclosed is a microprocessor based computer system utilizing either a DIMM or RIMM physical format processor element for the purpose of implementing a connection to an external switch, network, or other device. In a particular embodiment, connections may be provided to either the PCI, accelerated graphics port (&#x201c;AGP&#x201d;) or system maintenance (&#x201c;SM&#x201d;) bus for purposes of passing control information to the host microprocessor or other control chips. The field programmable gate array (&#x201c;FPGA&#x201d;) based processing elements have the capability to alter data passing through it to and from an external interconnect fabric or device.

Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format

A reconfigurable processor element incorporating both course and fine grained reconfigurable elements. In alternative implementations, the present invention may comprise a reconfigurable processor comprising both reconfigurable devices with fine grained logic elements and reconfigurable devices with course grained logic elements or a reconfigurable processor comprising both reconfigurable devices with fine grained elements and non-reconfigurable devices with course grained elements.

Reconfigurable processor element utilizing both coarse and fine grained reconfigurable elements

A multiprocessor computer architecture incorporating a plurality of programmable hardware memory algorithm processors ('MAP') in the memory subsystem. The MAP may comprise one or more field programmable gate arrays ('FPGAs') which function to perform identified algorithms in conjunction with, and tightly coupled to, a microprocessor and each MAP is globally accessible by all of the system processors for the purpose of executing user definable algorithms. A circuit within the MAP signals when the last operand has completed its flow thereby allowing a given process to be interrupted and thereafter restarted. Through the use of read only memory (&#x201c;ROM&#x201d;) located adjacent the FPGA, a user program may use a single command to select one of several possible pre-loaded algorithms thereby decreasing system reconfiguration time. A computer system memory structure MAP disclosed herein may function in normal or direct memory access (&#x201c;DMA&#x201d;) modes of operation and, in the latter mode, one device may feed results directly to another thereby allowing pipelining or parallelizing execution of a user defined algorithm. The system of the present invention also provides a user programmable performance monitoring capability and utilizes parallelizer software to automatically detect parallel regions of user applications containing algorithms that can be executed in the programmable hardware.

Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem

A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port ('APIP') added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses to and from this port, as well as the main microprocessor bus, are then arbitrated by the memory control circuitry forming a portion of the controller chip. In this fashion, both the microprocessors and the adaptive processors of the hybrid computing system exhibit equal memory bandwidth and latency. In addition, because it is a separate electrical port from the microprocessor bus, the APIP is not required to comply with, and participate in, all FSB protocol. This results in reduced protocol overhead which results higher yielded payload on the interface.

Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port

A reconfigurable processor module comprising hybrid stacked integrated circuit (&ldquo;IC&rdquo;) die elements. In a particular embodiment disclosed herein, a processor module with reconfigurable capability may be constructed by stacking one or more thinned microprocessor, memory and/or field programmable gate array (&ldquo;FPGA&rdquo;) die elements and interconnecting the same utilizing contacts that traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.

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Colorado Springs, CO, United States of America

Jon M Huppenthal