Fairchild Semiconductor Corporation

Jon Gladish

Joseph Andrew Yedinak

Gary M Dolny

Praveen Muraleedharan Shenoy

Mark L Rinehimer

Sampat Shekhawat

Douglas Joseph Lange

Thomas N Mathes

Jo Luo

Arthur Black

Sean T Tarlton

An integrated power stage device includes a switch node that is coupled to an output inductor. The integrated power stage device generates a monitor current that is a scaled version of the current through the output inductor. The integrated power stage device outputs a single-ended offset monitor current that is equal to the monitor current plus a DC offset current. A PWM controller senses the current through the output inductor by receiving a monitor voltage that is developed from the offset monitor current. The PWM controller generates a PWM signal in accordance with the sensed output inductor current to control a switching operation of a power switch of the integrated power stage device.

Integrated power stage device with offset monitor current for sensing a switch node output current

One embodiment provides A DC-DC converter system that includes a high side switch and a low side switch coupled to a power supply, each switch is configured to transition from an on state to an off state and from an off state to an on state to deliver current to an inductor and a load. This embodiment also includes low side driver circuitry configured to control the conduction state of the low side switch and configured to drive the low side switch with a first gate driving signal during a first mode of operation and with a second gate driving signal during a second mode of operation. The first gate driving voltage is stronger than the second gate driving signal and the second gate driving signal is configured to cause a slower switch transition of the low side switch compared to the first gate drive control signal.

Synchronous buck converter with dynamically adjustable low side gate driver

In one general aspect, a semiconductor structure can include a power transistor including a body region extending in a silicon region, a gate electrode insulated from the body region by a gate dielectric, a source region extending in the body region where the source region is of opposite conductivity type from the body region, a source interconnect contacting the source region, and a backside drain. The semiconductor structure can include an RC snubber monolithically integrated with the power transistor in a die. The RC snubber can include a snubber electrode insulated from the silicon region by a snubber dielectric such that the snubber electrode and the silicon region form a snubber capacitor.

Power device with monolithically integrated RC snubber

A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitance are adjusted dependent at least in part upon the PNP gain of the IGBT to maintain the potential difference between the gate and emitter at a level greater than the IGBT threshold voltage when the collector voltage reaches the bus voltage. This insures that the hole carrier concentration remains approximately equal to or greater than the drift region dopant concentration when the depletion layer punches through to the buffer region during the turn-off delay. Thus, the collector voltage overshoot and the rate of change of voltage and current are controlled, and electromagnetic interference is reduced, during turn off.

Quick punch through IGBT having gate-controllable DI/DT and reduced EMI during inductive turn off

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Forty Fort, PA, United States of America

Jon Gladish