Seagate Technology Incorporated

Other

Jon David Trantham

Riyan Alex Mendonsa

John West Dykes

Mark A Gaertner

Tim Rausch

Antoine Khoueir

Praveen Viraraghavan

Mohamad H El-Batal

Darshana H Mehta

Ian James Gilbert

Sangita Shreedharan Kalarickal

Matthew J Totin

Ryan James Goss

Brett Robert Herdendorf

Bruce Douglas Buch

Mehmet Fatih Erden

Kevin Arthur Gomez

Krishnan Subramanian

James Dillon Kiely

Edward Charles Gage

Wenzhong Zhu

Jason Bryce Gadbois

David Scott Ebsen

Todd Michael Lammers

Kenneth A Haapala

Joshua Ward Christensen

Anil Junuthula Reddy

Chiaming Yang

Bryan David Wyatt

Frank R Dropps

Robert Matousek

David Bruce Anderson

Hemant Vitthalrao Mane

Robert John Warmka

Ara Patapoutian

John Michael Bent

Timothy Richard Feldman

Steven Scott Williams

John Charles Duda

Monty Aaron Forehand

William Michael Radich

Jason Charles Jury

Barmeshwar Vikramaditya

Kevin Lee Van Pelt

Manuel A Offenberg

Charles William Thiesfeld

Kristofer Carlson Conklin

Peng Li

Won Choul Yang

Antanas Daugela

Andrei Dorobantu

Ajay Narayan Kulkarni

Scott Younger

Patrick Carl Fletcher

Varun Reddy Boddu

Kyaw Sin Maung

Christopher Thomas Cole

Aaron P Weyer

Kaizhong Gao

James Gary Wessel

Laszlo Hars

Ian Davies

Brian Thomas Edgar

Housan Dakroub

David Erich Tetzlaff

Robert Wayne Moss

Puskal Prasad Pokharel

John Edward Moon

Scott Edward Ryun

Raul Horacio Andruet

Raye Abdoulie Sosseh

Mai Ghaly

Jeffrey Vincent DeRosa

Srinivas Tadepalli

Mark Alan Heath

Donald Rozinak Beaver

Mehmet Faith Erden

William Preston Goodwill

Peng Peng

Timothy Ted Walker

Donald Preston Matthews, Jr

Paul William Burnett

Scott Robert Warmka

Darren Edward Johnston

Michael Joseph Steiner

Lijuan Zhong

Thomas Lee Schick

Dean Clark Wilson

Dale Herbert Erickson

Paul Michael Wiggins

Brian Dean Boling

Stephen S Huh

Nicholas James Dance

Vidur Parkash

Nicholas Paul Mati

Vidya Krishnamurthy

Yong Yang

Kevin Nghia Dao

Jay Rodger Elrod

Gina R Danner

The technology disclosed herein provides a memory blade including a plurality of fabric switches configured to receive commands from a plurality of host clients, an address decoder and tracker circuit communicatively connected to the fabric switches and configured to determine the source of commands received at the fabric switches an aggregator crossbar configured to provide bandwidth aggregation between host clients and a plurality of memory modules; and a buffer module configured to couple the commands from the plurality of host clients with the plurality of memory modules.

Fault-tolerant memory appliance

A processor may determine, for each subdevice of a set of subdevices of a storage enclosure device, one or more reliability measures of the subdevice. A processor may determine, based at least on the one or more reliability measures for the subdevices and a spatial layout rule, a set of striping groups that maximizes a reliability of the set of subdevices of the storage enclosure device, each of the striping groups including a respective subset of the set of subdevices, wherein the spatial layout rule prescribes a geometric layout of the subdevices within striping groups across the storage enclosure device. A processor may store output data of a data striping operation to a particular subset of subdevices associated with a particular striping group of the set of striping groups.

Wear leveling and grouping of drives based on position in chassis

Method and apparatus for managing a front-end cache formed of ferroelectric memory element (FME) cells. Prior to storage of writeback data associated with a pending write command from a client device, an intelligent cache manager circuit forwards a first status value indicative that sufficient capacity is available in the front-end cache for the writeback data. Non-requested speculative readback data previously transferred to the front-end cache from the main NVM memory store may be jettisoned to accommodate the writeback data. A second status value may be supplied to the client device if insufficient capacity is available to store the writeback data in the front-end cache, and a different, non-FME based cache may be used in such case. Mode select inputs can be supplied by the client device specify a particular quality of service level for the front-end cache, enabling selection of suitable writeback and speculative readback data processing strategies.

Intelligent management of ferroelectric memory in a data storage device

Described are hard disk drives (HDDs) operable for archival applications and utilizing the same mechanical and electrical design of conventional HDDs. The capacity of a conventional HDD may be extended by up to 25% to 40% or more by employing multiple write and/or read spins before declaring success in write and read processes. The multiple write and/or read spins are designed to address the lower reliability that would otherwise result from high density packing of the data, at the cost of reducing performance. The result is an HDD with lower performance at higher capacity without sacrificing reliability and without altering conventional HDD mechanical or electrical design.

High-density archival storage using conventional hard disk drive architecture

Apparatus and method for managing data in a non-volatile memory (NVM) having an array of ferroelectric memory cells (FMEs). A data set received from an external client device is programmed to a group of the FMEs at a target location in the NVM using a selected profile. The selected profile provides different program characteristics, such as applied voltage magnitude and pulse duration, to achieve desired levels of power used during the program operation, endurance of the data set, and latency effects associated with a subsequent read operation to retrieve the data set. The profile may be selected from among a plurality of profiles for different operational conditions. The ferroelectric NVM may form a portion of a solid-state drive (SSD) storage device. Different types of FMEs may be utilized including ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs).

Balancing power, endurance and latency in a ferroelectric memory

A data storage system for use in a high radiation environment runs first and second operating time counters to monitor a field-programmable, gate array (FPGA) configured as a storage controller. Based on the first operating time counter passing a first threshold, the FPGA is fully reprogrammed. Based on the second operating time counter passing a second threshold less than the first threshold, the FPGA is partially reprogrammed.

Radiation-resistant data storage device

A system on chip (SOC) integrated circuit device having an incorporated ferroelectric memory configured to be selectively refreshed, or not, depending on different operational modes. The ferroelectric memory is formed of an array of ferroelectric memory elements (FMEs) characterized as non-volatile, read-destructive semiconductor memory cells each having at least one ferroelectric layer. The FMEs can include FeRAM, FeFET or FTJ constructions. A read/write circuit writes data to the FMEs and subsequently reads back data from the FMEs responsive to respective write and read signals supplied by a processor circuit of the SOC. A refresh circuit is selectively enabled in a first normal mode to refresh the FMEs after a read operation, and is selectively disabled in a second exception mode so that the FMEs are not refreshed after a read operation. The FMEs can be used as a main memory, a cache, a buffer, an OTP, a keystore, etc.

System on chip (SOC) with processor and integrated ferroelectric memory

A data storage system can utilize one or more data storage devices that employ a solid-state non-volatile read destructive memory consisting of ferroelectric memory cells. A leveling strategy can be generated by a wear module connected to the memory with the leveling strategy prescribing a plurality of memory cell operating parameters associated with different amounts of cell wear. The wear module may monitor activity of a memory cell and detect an amount of wear in the memory cell as a result of the monitored activity, which can prompt changing a default set of operating parameters for the memory cell to a first stage of operating parameters, as prescribed by the leveling strategy, in response to the detected amount of wear.

Read destructive memory wear leveling system

A data storage chassis includes a plurality of data storage cartridges, and printed circuit board assembly (PCBA) electronics selectively connectable to one or more of the plurality of data storage cartridges. The data storage chassis also includes a wireless interface controller communicatively coupled to the PCBA electronics. The wireless interface controller facilitates wireless communication of data between the data storage chassis and a host using at least one frequency in a range of frequencies including fifth-generation (5G), millimeter, and sub-millimeter frequency ranges.

Wireless data storage devices and systems

A non-volatile memory (NVM) is formed of memory cells each having multiple ferroelectric memory elements (FMEs). Each FME stores data in relation to an electrical polarity of a recording layer formed of ferroelectric or anti-ferroelectric material. Each multi-FME memory cell is coupled to a set of external control lines activated by a control circuit in a selected order to perform program and/or read operations upon the FMEs. The FMEs may share a nominally identical construction or may have different constructions. Data are programmed and written responsive to the respective program/read responses of the FMEs. Constructions can include ferroelectric tunneling junctions (FTJs), ferroelectric random access memory (FeRAM), and ferroelectric field effect transistors (FeFETs). The NVM may form a portion of a data storage device, such as a solid-state drive (SSD).

Non-volatile memory cell with multiple ferroelectric memory elements (FMEs)

A data storage system for use in a high radiation environment includes an array of storage drives. Each storage drive includes a non-radiation-hardened drive controller, a non-radiation-hardened, non-volatile, storage medium, and a non-radiation-hardened volatile memory. The system includes a radiation-hardened storage controller coupled to the array. The radiation-hardened storage controller provides failure-resistant data redundancy among the storage drives of the array and provides host access to the array.

Apparatus and method for managing data in a processing system, such as but not limited to a data storage device such as a solid-state drive (SSD). A ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first construction and a second arrangement of FMEs of a different, second construction arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide pointers to point to each of the respective cache lines based on a time sequence of operation of the processor. Data sets can be migrated to the different arrangements by the controller as required based on the different operational characteristics of the respective FME constructions. The FMEs may be non-volatile and read-destructive. Refresh circuitry can be selectively enacted under different operational modes.

Stack register having different ferroelectric memory element constructions

A memory device formed of ferroelectric field effect transistors (FeFETs). The memory device can be used as a front end buffer, such as in a data storage device having a non-volatile memory (NVM). A controller can be configured to transfer user data between the NVM and an external client (host) via the buffer. The FeFETs can be arranged in a two-dimensional (2D) or a three-dimensional (3D) array. A monitor circuit can be used to monitor operation of the FeFETs. An optimization controller can be used to adjust at least one operational parameter associated with the FeFETs responsive to the monitored operation by the monitor circuit. The FeFETs may require a refresh operation after each read operation. A power down sequence can involve a read operation without a subsequent refresh operation to wipe the FeFETs, the read operation jettisoning the data read from the buffer memory.

Front end buffer having ferroelectric field effect transistor (FeFET) based memory

A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.

Intelligent cache with read destructive memory cells

A data storage system can employ a read destructive memory configured with multiple levels. A non-volatile memory unit can be programmed with a first logical state in response to a first write voltage of a first hysteresis loop by a write controller prior to being programmed to a second logical state in response to a second write voltage of the first hysteresis loop, as directed by the write controller. The first and second logical states may be present concurrently in the non-volatile memory unit and subsequently read concurrently as the first logical state and the second logical state.

Data storage with multi-level read destructive memory

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Chanhassen, MN, United States of America

Jon David Trantham