Rf Micro Devices, Inc.

Jon D Jorgenson

David C Dening

Victor E Steel

Michael R Kay

Milind Shah

Khoi Tam Vu

Steve Dorn

Yang Rao

Ruediger Bauder

Thomas Scott Morris

Edward T Spears

Ulrik Riis Madsen

David Durgin Coons

Curtis A Barratt

Scott McCall

The present invention is an RF cancellation circuit located between the output of a power amplifier and downstream circuitry, such as a transmitting antenna. The RF cancellation circuit cancels reflections resulting from antenna impedance mismatches, thereby presenting a constant load impedance to the output of the power amplifier. The RF cancellation circuit extracts a portion of the reflected signal, phase-shifts by 180 degrees and amplifies the extracted portion of the reflected signal to create a cancellation signal, and then cancels the balance of the reflected signal by adding in the cancellation signal. Directional circuitry is used to process the reflected signals without interfering with normal transmitted signals. Presenting a constant load impedance to the output of the power amplifier helps facilitate compliance with total radiated power into load mismatch specifications.

Reflection cancellation circuit for a radio frequency power amplifier

Pilot switch circuitry coupled across first and second terminals of a microelectromechanical system (MEMS) switch is provided to reduce or eliminate arcing between a cantilever contact and a terminal contact when the MEMS switch is opened or closed. The pilot switch circuitry establishes a common potential at the first and second terminals prior to, and preferably until, the cantilever contact and terminal contact come into contact with one another when the MEMS switch is closed. The pilot switch circuitry may also establish a common potential at the first and second terminals prior to, and preferably after, the cantilever contact and terminal contact separate from one another when the MEMS switch is opened.

Pilot switch

A circuit board having an embedded inductor and a process for making the circuit board is provided. In general, the process begins by providing a core structure including a dielectric core layer and a first metal layer on a top surface of the dielectric core layer. The first metal layer is etched to form first inductor windings. A material, such as an epoxy material, including magnetic filler material is deposited over the first inductor windings. Thereafter, a prepreg layer is placed over and attached to the material deposited over the first inductor windings to form the circuit board having the embedded inductor.

Circuit board embedded inductor

A system is provided for adjusting an output power of a multi-stage power amplifier by controlling a supply voltage provided to one or more output amplifier stages of the power amplifier using a switching DC&#x2014;DC converter. In general, the system includes a power amplifier including an input amplifier stage and one or more output amplifier stages coupled in series with the input amplifier stage. The one or more output amplifier stages receive a variable supply voltage from switching DC&#x2014;DC conversion circuitry. The switching DC&#x2014;DC conversion circuitry provides the variable supply voltage based on an adjustable power control signal. By controlling the variable supply voltage provided to the one or more output stages, the switching DC&#x2014;DC conversion circuitry controls an output power of the power amplifier based on the adjustable power control signal.

Power amplifier control using a switching power supply

An adaptive manufacturing process for a Film Bulk Acoustic Resonator (FBAR) tests the FBAR circuit during manufacturing to determine a resonant frequency thereof. Reactive tuning elements may be adjusted as needed depending on the testing to change the resonant frequency to a desired resonant frequency. In an exemplary embodiment, predetermined masks may be applied to modify the tuning elements.

Adaptive manufacturing for film bulk acoustic wave resonators

The present invention provides for attaching a Gallium Arsenide (GaAs) semiconductor die to a package using bumps formed over a metallic heat sink covering the output transistor area of the semiconductor die. In general, one or more bumps are formed on the metallic heat sink, thereby eliminating stress on the bumps caused by stress risers on the surface of the semiconductor die. In addition, the upper and lower surfaces of the bumps are substantially planar, thereby maximizing contact with the semiconductor die and the package and allowing maximum heat transfer. The planarization is due to the conforming contact surface of the solder. The combination of the bumps and the metallic heat sink provide an efficient way to reduce the thermal and electrical impedance of the die. In one embodiment, the bumps are substantially copper. In another embodiment, the bumps are substantially gold.

Method of fabricating posts over integrated heat sink metallization to enable flip chip packaging of GaAs devices

The present invention eliminates the need for complex impedance networks or parallel amplification stages for multi-mode mobile terminals. A wideband power amplifier is configured to amplify signals in different frequency bands corresponding to different operating modes. The supply voltage of the wideband power amplifier is adjusted in light of the load impedance of radiating circuitry to achieve a desired output power for the respective operating modes.

Single output stage power amplification for multimode applications

An amplifier provides two or more selectively enabled amplifier segments allowing a source signal to be amplified with a selectable output power. A bias circuit responsive to a bias control signal enables selectable combinations of one or more amplifier segments, thus allowing selection of a desired output power. Selecting a desired output signal power via the bias control signal corresponds to selecting an overall amplifier quiescent current that decreases with decreasing output signal power. Thus, the amplifier permits a controlling system, such as a mobile terminal (e.g., cellular telephone) to amplify a transmit signal with a selectable transmit signal output power and corresponding level of amplifier quiescent power consumption. Preferably, each segment comprises one or more transistor amplification stages which, when enabled by the bias circuit, are biased to permit maximum power linear amplification for the transmit signal.

Segmented power amplifier and method of control

Adaptive manufacturing of semiconductor circuits

A bias network uses resistive biasing, active biasing and current mirror biasing in combination to enhance RF power amplifier linearity and efficiency by forming a bias network that provides temperature compensation, minimizes current drain requirements for the Vbias source and reduces the level of RF linear amplifier quiescent current.

Bias network for high efficiency RF linear power amplifier

A high efficiency multiple power level power amplifier has a PIN diode network that selectively associates an impedance transformation network with an interstage impedance matching network to maintain desired gain and linearity characteristics for the power amplifier at different output power levels. The PIN diode network in the off mode (high power), has a high breakdown voltage and high series resistance thereby reducing distortion components. The PIN diode network in the on mode (low power), has a low series resistance thereby reducing insertion losses.

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Greensboro, NC, United States of America

Jon D Jorgenson