Advanced Micro Devices Corporation

Freescale Semiconductor,inc.

Jon D Cheek

Derick J Wristers

Mark I Gardner

Daniel Kadosh

James F Buller

H Jim Fulford

Mark W Michael

John G Pellerin

John J Bush

Fred N Hause

Robert Louis Dawson

Scott D Luning

Anthony John Toprac

Andrew Michael Waite

James N Pan

Frank Kelsey Baker, Jr

Michael P Duane

Marilyn I Wright

David E Brown

Brad T Moore

Mark I Garnder

Chad Weintraub

Frederick N Hause

Srikanteswara Dakshina-Murthy

James David Burnett

Basab Bandyopadhyay

Thomas E Spikes, Jr

Douglas J Bonser

Byoung W Min

Venkat Kolagunta

Mark Brandon Fuselier

Derrick J Wristers

William A Whigham

Johannes F Groschopf

Antonio Torres Garcia

A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells () prior to the formation of high-k metal gate electrodes for CMOS transistors () using a planarized dielectric layer () and protective mask () to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Embedded NVM in a HKMG process

A semiconductor device comprising a substrate having a first crystal orientation is provided. A first insulating layer overlies the substrate and a plurality of silicon layers overlie the first insulating layer. A first silicon layer comprises silicon having a second crystal orientation and a crystal plane. A second silicon layer comprises silicon having the second crystal orientation and a crystal plane that is substantially orthogonal to the crystal plane of the first silicon layer. Because holes have higher mobility in the (110) plane than the (100) plane, while electrons have higher mobility in (100) plane than the (110) plane, semiconductor device performance can be enhanced by the selection of silicon layers with certain crystal plane orientations. In addition, a method of forming a semiconductor device is provided. A silicon-on-insulator structure comprising a first silicon substrate having a first crystal orientation with a first insulating layer formed thereon and a first silicon layer having a second crystal orientation and a crystal plane overlying the first insulating layer is bonded to a second silicon substrate. The second silicon substrate has the second crystal orientation and a crystal plane and a second insulating layer formed thereon. The second silicon substrate comprises a line of defects created by implanting hydrogen ion into the second silicon substrate. The crystal plane of the second silicon substrate is oriented substantially orthogonal to the crystal plane of the first silicon layer. The second silicon substrate is split and removed along the line of defects leaving behind the second insulating layer and a second silicon layer on the silicon-on-insulator structure. A plurality of devices with different crystal orientations can be subsequently formed on a single, planar silicon-on-insulator structure by selectively etching the silicon-on-insulator structure down to silicon layers of different crystal orientations, growing selective epitaxial silicon layers in the etched regions, and subsequently planarizing the silicon-on-insulator structure by chemical-mechanical polishing.

Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers

A method for making a semiconductor device, comprising (a) providing a structure comprising a gate electrode () disposed on a substrate (); (b) creating first () and second () pre-amorphization implant regions in the substrate such that the first and second pre-amorphization implant regions are asymmetrically disposed with respect to said gate electrode; (c) creating first () and second () spacer structures adjacent to first and second sides of the gate electrode, wherein the first and second spacer structures overlap the first and second pre-amorphization implant regions; and (d) creating source () and drain () regions in the substrate adjacent, respectively, to the first and second spacer structures.

Methodology to reduce SOI floating-body effect

A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

Low-power multiple-channel fully depleted quantum well CMOSFETs

An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

Interlayer dielectric under stress for an integrated circuit

A semiconductor device comprising a substrate having a first crystal orientation and an insulating layer overlying the substrate is provided. A plurality of silicon layers are formed overlying the insulating layer. A first silicon layer comprises silicon having the first crystal orientation and a second silicon layer comprises silicon having a second crystal orientation. In addition, a method of forming a semiconductor device providing a silicon-on-insulator structure comprising a substrate with a silicon layer overlying the substrate and a first insulating layer interposed therebetween is provided. An opening is formed in a first region of the silicon-on-insulator structure by removing a portion of the silicon layer and the first insulating layer to expose a portion of the substrate layer. Selective epitaxial silicon is grown in the opening. A second insulating layer is formed in the silicon grown in the opening to provide an insulating layer between the grown silicon in the opening and the substrate.

Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device

An insulated gate field effect transistor having reduced gate-drain overlap and a method for manufacturing the insulated gate field effect transistor. A gate structure is formed on a major surface of a semiconductor substrate. A source extension region and a drain extension region are formed in a semiconductor material using an angled implant. The source extension region extends under the gate structure, whereas the drain extension region is laterally spaced apart from the gate structure. A source region is formed in the semiconductor substrate and a drain region is formed in the semiconductor substrate, where the source and drain regions are laterally spaced apart from the gate structure. A source-side halo region is formed in the semiconductor substrate adjacent the source extension region.

Method of manufacturing a semiconductor component

A method for offsetting silicide on a semiconductor device having a polysilicon gate electrode, source and drain regions in a substrate, and source and drain extensions in the substrate, employs a titanium nitride sidewall spacer on the sidewalls of the polysilicon gate electrode. The titanium nitride sidewall spacer prevents silicide growth on top of the source and drain extensions during a salicidation process. The titanium nitride sidewall spacers are then removed by an etching process that does not etch the silicide regions formed in the source and drain regions and the polysilicon gate electrode. Following removal of the titanium nitride sidewall spacers, a low k interlevel dielectric layer or a stress liner may be deposited on top of the devices to enhance device performance.

Method for offsetting a silicide process from a gate electrode of a semiconductor device

STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 &#x212b;. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.

Method of reducing STI divot formation during semiconductor device fabrication

An insulated gate field effect semiconductor component having a source-side halo region and a method for manufacturing the semiconductor component. A gate structure is formed on a semiconductor substrate. The source-side halo region is formed in the semiconductor substrate. After formation of the source-side halo region, spacers are formed adjacent opposing sides of the gate structure. A source extension region and a drain extension region are formed in the semiconductor substrate using an angled implant. The source extension region extends under the gate structure, whereas the drain extension may extend under the gate structure or be laterally spaced apart from the gate structure. A source region and a drain region are formed in the semiconductor substrate.

Method for manufacturing a semiconductor component having an early halo implant

The present invention is generally directed to various methods of forming metal silicide regions on transistors based upon gate critical dimensions. In one illustrative embodiment, the method comprises forming a layer of refractory metal above a plurality of transistors, reducing a thickness of at least a portion of the layer of refractory metal above at least some of the transistors and performing at least one anneal process to form metal silicide regions above the transistors. In another illustrative embodiment, the method comprises forming a layer of refractory metal above the plurality of transistors, reducing the thickness of the layer of refractory metal above a first of the transistors having a gate electrode with a critical dimension that is less than a critical dimension of a gate electrode structure of another of the plurality of transistors, and performing at least one anneal process to form metal silicide regions on the plurality of transistors. In yet another illustrative embodiment, the method comprises forming a layer of refractory metal to an original thickness above a plurality of transistors, reducing the original thickness of a portion of the layer of refractory metal above at least some of the transistors to define a layer of refractory metal having multiple thicknesses, and performing at least one anneal process to convert portions of the layer of refractory metal having multiple thicknesses to metal silicide regions on the transistors.

Method of forming silicide layers over a plurality of semiconductor devices

A method of forming source/drain regions in a semiconductor device is provided. In one illustrative embodiment, the method comprises forming a gate electrode above a semiconducting substrate, forming source/drain regions in the substrate adjacent the gate electrode by performing at least the following steps: performing two ion implantation processes to form source/drain extensions for the device and performing a third ion implantation process to further form source/drain regions for the device. Various N-type and P-type dopant atoms such as arsenic, phosphorous, boron and boron difluoride may be used with the present invention.

Method of forming source/drain regions in a semiconductor device

A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions. The metal gate electrode is aligned using a polysilicon alignment structure, which permits high temperature processing before the metal is deposited.

Growing community of inventors

Round Rock, TX, United States of America

Jon D Cheek