Silicon Graphics, Incorporated

Jon C Gibbons

Steven C Miller

Michael Brian Galles

David M Parry

A data synchronizer ( ) receives a data ready signal ( ) at a selector ( ). The selector ( ) selects either the data ready signal ( ) or a delayed version of the data ready signal ( ) in response to a speed select signal ( ) determined according to a clock speed of a receive core clock ( ). The selector ( ) provides a select signal ( ) to a first latch unit ( ) and a second latch unit ( ). The first latch unit ( ) generates a latched select signal (A) that is provided as a receive data valid signal ( ) by a signal generator ( ) in response to a slow clock rate for the receive core clock ( ). The second latch unit ( ) generates a delayed select signal (B) that is used by the signal generator ( ) to remove an extra width inserted into the latched select signal (A) prior to providing the receive data valid signal ( ) in response to a fast clock rate for the receive core clock ( ).

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San Francisco, CA, United States of America

Jon C Gibbons