International Business Machines Corporation

Jon A Patrick

Roger W Fleury

Robert K Leidy

Jeffrey Scott Miller

Rosemary A Previti-Kelly

A method of dynamically switching the voltage screen test parameters without falsely rejecting over stressing short channel length devices. Protection to more vulnerable devices is provided by determining the speed of the die prior to the voltage test screen, segregating the devices based on operational speed performance. A lower voltage is effectively applied during wafer probe test to the faster devices, which directly correspond to the population of short channel devices. Device speed is acquired by measuring the drain-to-source current of each FET, and dividing the resultant sum by the device gate channel width. The device with the higher values represent the faster devices. Alternatively, since faster devices draw more current, the supply current specification may be adjusted based on operational speed measurements.

Method of dynamically switching voltage screen test levels based on initial device parameter measurements

This invention teaches an apparatus and method for determining a more efficient quality assurance or reliability test screen without falsely rejecting, i.e., over stressing, short channel length devices during voltage stress test screening. Short channel lengths devices fabricated on a semiconductor wafer have a higher tendency to fail at voltage levels that would otherwise not harm long channel length devices. The failures, however, are not related to device defects. Protection to the more vulnerable devices is provided by determining the speed of the die prior to the voltage test screen, thus, segregating the devices based on operational speed performance. Next, a lower voltage is effectively applied during wafer probe test to the faster devices, which directly correspond to the population of short channel devices. A preferred measurement for device speed entails measuring the drain-to-source current of each FET, and dividing the resultant sum by the device gate channel width. The devices with the higher values represent the faster devices. Alternatively, since faster devices draw more current, the supply current specification may be adjusted based on operational speed measurements, for fast and slow devices accordingly.

Dynamically switched voltage screen

Method for determining a more efficient quality assurance or reliability test screen without falsely rejecting, i.e., over stressing, short channel length devices during voltage stress test screening. Short channel lengths devices fabricated on a semiconductor wafer have a higher tendency to fail at voltage levels that would otherwise not harm long channel length devices. The failures, however, are not related to device defects. Protection to the more vulnerable devices is provided by determining the speed of the die prior to the voltage test screen, thus, segregating the devices based on operational speed performance. Next, a lower voltage is effetively applied during wafer probe test to the faster devices, which directly correspond to the population of short channel devices.

Method for testing semiconductor devices

A method and structure for reducing short circuits in semiconductor devices is disclosed. A three layer interlevel dielectric structure is formed over a semiconductor substrate, which typically comprises a first metallization level, M1. The three layer dielectric includes a first insulator layer, a middle spin-on glass (SOG) layer, and a top second insulator layer. The spin-on glass fills defects in the surface of the first insulator layer created during planarization using chemical-mechanical-polishing (CMP). Prior to deposition of the second insulator, a first via is etched through the SOG film and the first insulator layer to expose a portion of the semiconductor substrate, typically a conductive metal. A conductive metal is deposited into the first via and planarized to form a metal interconnection stud. Because the surface defects are filled and covered with the SOG film, none of the deposited metal enters the defects, and short circuits with the stud are greatly reduced. The second insulator layer is deposited onto the SOG film and the end of the metal interconnection stud. A second via is formed through the second insulator material to the stud end, and the second via is available for subsequent deposition of a conductive metal to provide electrical connection to the semiconductor substrate.

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Jericho, VT, United States of America

Jon A Patrick