Applied Micro Circuits Corporation

Motorola Corporation

Apple Inc.

Jon A Loschke

Timothy A Olson

Terrence Matthew Potter

Charley Michael Parks

Terence M Potter

James S Blomgren

Robert A Drebin

Kenneth W Jones

Mark Franklin

Douglas C Youngwith

A system and method for efficiently accessing operands in a datapath. An apparatus includes a data operand register file and an execution pipeline with multiple stages. In addition, the apparatus includes a result bypass cache configured to store data results conveyed by at least the final stage of the execution pipeline stage. Control logic is included which is configured to determine whether source operands for an instruction entering the pipeline are available in the last stage of the pipeline or in the result bypass cache. If the source operands are available in the last stage of the pipeline or the result bypass cache, they may be obtained from one of those locations rather than reading from the register file. If the source operands are not available from the last stage or the result bypass cache, then they may be obtained from the data operand register file.

Result bypass cache

A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR.

Method for repairing a speculative global history record

System and method for repairing a speculative global history record

Provided is a means for accessing multiple entries from a branch history table (BHT) in a single clock cycle, in the context of pipelined instruction processing. In a first clock cycle, a plurality of conditional branch instructions is fetched. A value is accessed from a global history record (GHR) of conditional branch resolutions and predictions for a fetched conditional branch instruction. An associated instruction address is hashed with a left-shifted GHR value. The result is used to access a word in an indexed BHT stored in a single-port random access memory (RAM). The word comprises a branch direction count for the plurality of fetched conditional branch instructions. In a second clock cycle a conditional branch instruction is executed at an execute stage and the BHT is written with an updated branch direction count in response to a resolution of the executed conditional branch instruction.

Microprocessor system for simultaneously accessing multiple branch history table entries using a single port

A system and method are provided for updating a global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts a microprocessor instruction of consecutive operations, including a conditional branch operation with an associated branch address, at a first stage in a pipelined microprocessor execution process. A global history record (GHR) of conditional branch resolutions and predictions is accessed and hashed with the branch address, creating a first hash result. The first hash result is used to access an indexed branch history table (BHT) of branch direction counts and the BHT is used to make a branch prediction. If the branch prediction being 'taken', the current GHR value is left-shifted and hashed with the branch address, creating a second hash result which is used in creating an updated GHR.

Global history branch prediction updating responsive to taken branches

System and method for speculative global history prediction updating

A circuit and method is provided for implementing a content addressable memory circuit (100) in which an output word is produced which corresponds to the content of a reference word containing an ATM header. According to a first aspect, a binary search logic circuit (104) binarily searches the memory array (101) to find a match word whose content is equal to that of the reference word. Output signals indicate either that a match has been found or that the binary searching of the memory array (101) should continue at addresses either above or below the location address of the match word. According to a second aspect, the content addressable memory circuit (100) performs a concurrent search of switching identifiers, virtual circuit identifiers and virtual path identifiers, to determine if a virtual path connection or virtual circuit connection exists for an ATM header.

Apparatus and method for concurrent search content addressable memory

A circuit and method is provided for implementing a content addressable memory circuit (100) in which at least one output word is produced which corresponds to the content of a match word. A binary search logic circuit (103) binarily searches the memory array (101) to find a match entry with multiple words whose content is equal to that of an input value with multiple words. The amount of words in each match entry is user programmable and defined at startup. The CAM (100) is capable of masking out words to be compared or outputted and allows overlapping of words to be compared and outputted. Output signals indicate whether a match has been found.

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Austin, TX, United States of America

Jon A Loschke