Netspeed Systems

Other

Intel Corporation

Future Wei Technologies, Inc.

Baya Systems, Inc.

Joji Philip

Sailesh Kumar

Eric Norige

Joseph Rowlands

Sundari Mitra

Mahmud Hassan

Joe Rowlands

Nishant Rao

William C Lynch

William John Bainbridge

Michel Hanna

Eric A Norige

Dawn Maxon

Joseph B Rowlands

James Aldis

Swapnil Lotlikar

A method for a snoop filter includes using binary encodings and vector encodings to represent owner and sharers of cache lines of a cache. The vector encodings can be split across the multiple ways of the snoop filter via a vector range identifier and a common tag. Further, only vector ranges having at least one sharer from the sharers are allocated a way from the multiple ways.

Snoop filter sharer vector expansion

A system comprising a network-on-chip (NOC) fabric comprising a plurality of routes to communicate data between a plurality of agents; a plurality of built-in self-test (BIST) generators, wherein a BIST generator of the plurality of BIST generators is coupled between an agent of the plurality of agents and the NOC fabric and is to transmit at least one test pattern through the NOC fabric; and a plurality of BIST checkers, wherein a BIST checker of the plurality of BIST checkers is coupled between the agent of the plurality of agents and the NOC fabric and is to receive at least one test pattern through the NOC fabric from at least one of the plurality of BIST generators and to verify whether the at least one test pattern was transmitted correctly through the NOC fabric.

Built-in self-test for network on chip fabric

Aspects of the present disclosure relate to page locality based memory access request processing in a network-on-chip (NoC) architecture. In an example implementation, the proposed method includes determining, at an arbitrator, while selecting a NoC agent from a plurality of NoC agents for request processing for a forthcoming round, if current NoC agent of current round is processing a packet stream and if said packet stream is completely processed at the end of said current round, wherein processing of the packet stream enables cluster requests to be processed at same part of said memory and enhances page locality; and re-selecting, at said arbitrator, said current NoC agent as the NoC agent for the forthcoming round if said packet stream processing is not completed at the end of said current round, so as to enable said current NoC agent to complete processing of said packet stream in said forthcoming round.

Enhanced page locality in network-on-chip (NoC) architectures

The present disclosure relates to a bandwidth weighting mechanism based NoC configuration/constructions for packet routing. In an aspect, the present disclosure relates to a method for packet routing in a circuit architecture, wherein the method includes the steps of managing, at a router of the circuit architecture, one or more catch-up bits, each of the one or more catch-up bits indicating that the router has reset a round of round-robin based packet routing without allowing an agent corresponding to the each of the one or more catch-up bits to complete its respective round; and allowing, by the router, the agent to continue its respective round in catch-up state such that upon completion of the respective round, the agent is switched to normal state.

Bandwidth weighting mechanism based network-on-chip (NoC) configuration

Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.

Interface virtualization and fast path for Network on Chip

Interface virtualization and fast path for network on chip

Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel NoC interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system.

Heterogeneous channel capacities in an interconnect

Example implementations described herein are directed to a micro-architecture of NoC router clocking which allows for a flexible Globally Asynchronous Locally Synchronous (GALS) implementation. The example implementations allow arbitrary clock domain partitions to be defined across the system. The example implementations further involve allowing the components of the NoC to be configured by the user through a NoC generation system to achieve the desired arbitrary clock domain partitioning.

Multiple clock domains in NoC

Aspects of the present disclosure relates to methods, computer readable mediums, and NoC architectures/systems/constructions that can automatically mark and configure some channel of a NoC as store-and-forward channels, and other channels of the NoC as cut-through channels, and can further resize the buffers/channels based on the given NoC specification and associated traffic profile. An aspect of the present disclosure relates to a method for configuring a first set of plurality of channels of a NoC as store-and-forward channels, and configuring a second set of plurality of channels of the NoC as cut-through channels based on the determination of idle cycles in a given NoC specification and associated traffic profile.

Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip

Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve automatically generating internal dependency specification of a system component based on dependencies between incoming/input and outgoing/output interface channels of the component. Dependencies between incoming and outgoing interface channels of the component can be determined by blocking one or more outgoing interface channels and evaluating impact of the blocked outgoing channels on the incoming interface channels. Another implementation described herein involves determining inter-component communication dependencies by measuring impact of a deadlock on the blocked incoming interface channels of one or more components to identify whether a dependency cycle is formed by blocked incoming interface channels.

Identification of internal dependencies within system components for evaluating potential protocol level deadlocks

A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers.

Hierarchical asymmetric mesh with virtual routers

Example implementations described herein are directed to a configurable building block, such as a router, for implementation of a Network on Chip (NoC). The router is parameterized by a software layer, which can include the number of virtual channels for a port, the number of ports, the membership information of the virtual channels, clock domain, and so forth. The router may further be configured to implement arbitration techniques and flit processing techniques based on the parameters specified by the software layer.

Configurable router for a network on chip (NoC)

Example implementations are directed to more efficiently delivering a multicast message to multiple destination components from a source component. Multicast environment is achieved with transmission of a single message from a source component, which gets replicated in the NoC during routing towards the destination components indicated in the message. Example implementations further relate to an efficient way of implementing multicast in any given NoC topology, wherein one or more multicast trees in the given NoC topology are formed and one of these trees are used for routing a multicast message to its intended destination components mentioned therein.

Growing community of inventors

San Jose, CA, United States of America

Joji Philip