Altera Corporation

Johnson Tan

Chiakang Sung

Joseph Huang

Yan Chong

Philip Pan

Michael H M Chu

Philip Clarke

Andrew J Bellis

Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and output circuits to self-calibrate by compensating for temperature and voltage changes in an efficient manner, without the need for device reconfiguration. Calibration settings can be maintained while new calibration settings are loaded. Skew between clock and data signals, as well as among multiple data signals, can be reduced. Dynamic control is achieved while consuming only a minimal resources including route paths.

Dynamic control of memory interface timing

A memory cell of a programmable device includes a memory partitioning circuit to partition a multiple port memory device into one or more single port memory partitions. The memory partitioning circuit prevents cross addressing by setting the value of one or more address lines of each memory port to a fixed value. The memory partitioning circuit holds address lines at their required values during the programmable device's normal, clear, and reset modes of operation. The behavior of the memory partitioning circuit is set by a portion of a device configuration used to configure the programmable device. The memory partitioning circuit is connected between a memory cell's address register and row or column decoders used to access the multiple port memory device. The memory partitioning circuit can also perform bit-wise inversion operations on portions of the memory addresses.

Address control for efficient memory partition

Techniques are provided for recycling addresses in memory blocks. Address signals in memory blocks are stored temporarily in a set of parallel coupled address registers. The address registers transfer the address signals to an address decoder block, which decodes the address signals. The address decoder block transfers the decoded addresses to a memory array. A stall state occurs when the cache memory block needs a new set of data to replace the old set of data. Address signals are stored in the address registers during the stall state by coupling each register's output to its data input using a series of multiplexers. The multiplexers are controlled by an address stall signal that indicates the onset and the end of a stall state. After the end of a stall state, the address registers store the next address signal received at the memory block.

Techniques for implementing address recycling in memory circuits

Techniques for preloading data into memory blocks on a programmable circuit are provided. Memory blocks on the a programmable circuit each have dedicated circuitry that loads data into the memory block. The dedicated circuit also generates memory addresses used to load the data into the memory block. The dedicated circuitry associated with each memory block reduces demand on the routing resources. A user can preload data into the memory blocks prior to user mode. A user can also prevent data from being preloaded into one or more of the memory blocks prior to user mode. By allowing the user to program some or all of the memory blocks prior to user mode, the time needed to a program the memory blocks prior to user mode can be substantially reduced.

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San Jose, CA, United States of America

Johnson Tan