Cadence Design Systems, Inc.

Johnson Chan Limqueco

Krishna Prasad Belkhale

Hong Li

Devadas Varma

Provided are a method, article of manufacture, and apparatus for estimating delays of networks. An automated design system comprises a computer configured to identify a critical path in a network, calculate a delay for the technology-mapped version of the network, calculate a delay for the technology-independent version of the network, calculate a scale factor from the technology-mapped and technology-independent delays, and apply the scale factor to all the delays in the technology-independent network.

Delay estimation for restructuring

Delay estimation for restructuring the technology independent circuit

Two time budgeting techniques are provided that are suitable for early and late integrated circuit design phases, respectively. During the early design phase, both the positive and negative slack paths are time budgeted, such that a positive slack path cannot become a negative slack path after budget generation. If all the budget constraints are met by resynthesis for all circuit modules, then the technique guarantees that the final design, when assembled, meets all time constraints. During the late design phase, convergence is guaranteed. Further, synthesis runs for sub-modules focus initially on the worst critical path.

Method and apparatus for performing both negative and positive slack time budgeting and for determining a definite required constraint during integrated circuit design

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Sunnyvale, CA, United States of America

Johnson Chan Limqueco