Other

The Hong Kong University of Science and Technology

Fuji Electric Co., Ltd.

Zhong Shan Honson Electronic Technologies Limited

Johnny Kin On Sin

Xianda Zhou

Rongxiang Wu

Chun Wai Ng

Yuichi Onozawa

Jiajin Liang

Wentao Yang

Shu Yuen Ron Hui

Masashi Akahane

Yoshiaki Toyoda

Hitoshi Sumida

Kei May Lau

Kaname Mitsuzuka

Chik Patrick Yue

Lulu Peng

Xiangming Fang

Hao Feng

Song Yuan

Shuk-Wa Fung

Wai Yee Liu

Iftikhar Ahmed

At edge termination region, a trench is disposed near an interface of an active region. Inside the trench, an embedded insulating film is embedded, and inside the embedded insulating film, a FP long in a direction of depth is disposed. The FP curves outwardly away from an inner sidewall of the trench as a depth from a base front surface increases. At least near a bottom end of the FP, a distance between the FP and the inner sidewall of trench is greater than a width of the groove. The FP is connected to a front surface electrode that extends on the embedded insulating film. As a result, breakdown voltage can be enhanced, adverse effects of the surface charge can be reduced, and chip size can be further reduced.

Semiconductor device and method of manufacturing semiconductor device

An insulated gate bipolar transistor (IGBT) device and a method for manufacturing the same are provided. The present disclosure relates to power semiconductor devices. In order to relieve the problem of wafer warping caused by trench stress in an IGBT manufacturing process without affecting other performance parameters of the IGBT, it provides the following technical solution: optimizing the design of arrangement densities and arrangement regions of device trenches. The present disclosure can alleviate the problem of wafer warping caused by trench stress in the IGBT manufacturing process, improve the product yield of IGBT chips, and enhance the latch-up immunity of the IGBT, so that the IGBT is more robust and durable.

Insulated gate bipolar transistor device and method for manufacturing the same

The present invention discloses a rugged power semiconductor field effect transistor structure, and through a special design, it solves the problem that the activation under a transient condition may result in failures on the device, so that there is no parasitic BJT, and thus the device is more rugged.

Solid power semiconductor field effect transistor structure

A structure and a manufacturing method of a power semiconductor device are provided. A structure of thin semi-insulating field plates () located between metal electrodes () at the surface of the power semiconductor device is provided. The thin semi-insulating field plates () are formed by depositing before metallization and annealing after the metallization. The present invention can be used in lateral power semiconductor devices and vertical power semiconductor devices.

Field plate structure for power semiconductor device and manufacturing method thereof

At edge termination region, a trench is disposed near an interface of an active region. Inside the trench, an embedded insulating film is embedded, and inside the embedded insulating film, a FP long in a direction of depth is disposed. The FP curves outwardly away from an inner side wall of the trench as a depth from a base front surface increases. At least near a bottom end of the FP, a distance between the FP and the inner side wall of the trench is greater than a width of the groove. The FP is connected to a front surface electrode that extends on the embedded insulating film. As a result, breakdown voltage may be enhanced, adverse effects of the surface charge may be reduced, and chip size may be further reduced.

The present invention generally relates to a structure and manufacturing of a power field effect transistor (FET). The present invention provides a planar power metal oxide semiconductor field effect transistor (MOSFET) structure and an insulated gate bipolar transistor (IGBT) structure comprising a split gate and a semi-insulating field plate. The present invention also provides manufacturing methods of the structures.

Split gate power semiconductor field effect transistor

An isolator is configured by a transmission circuit, a transformer, and a reception circuit. A first coil of the transformer is disposed on a back surface of a first semiconductor substrate; a transmission circuit and a second coil of the transformer are disposed on a front surface. The first coil is embedded within a coil trench, is led out through an embedded via-metal-film to a substrate front surface, and is electrically connected to the transmission circuit. The second coil is disposed on an insulating layer of the substrate front surface. The reception circuit is disposed on a front surface of a second semiconductor substrate. The second coil and the reception circuit are electrically connected to each other by connecting first and third electrode pads disposed respectively on the front surfaces of the first and second semiconductor substrates through wires.

Isolator and method of manufacturing isolator

Provided in the present invention is a trench gate power MOSFET (TMOS/UMOS) structure with a heavily doped polysilicon source region. The polysilicon source region is formed by deposition, and a trench-shaped contact hole is used at the source region, in order to attain low contact resistance and small cell pitch. The present invention may also be implemented in an IGBT.

Trench gate power semiconductor field effect transistor

A lighting device is provided. The lighting device includes a substrate, integrated circuits (), embedded passive components (), and a lighting component (), the device being arranged in an architecture having three layers: an integrated circuits layer () including the integrated circuits (), wherein the integrated circuits layer () is integrated on a first side of the substrate; an embedded passive components layer () including the embedded passive components (), wherein the embedded passive components () are embedded in grooves formed in the substrate and wherein the embedded passive components are connected to the integrated circuits () through vias () in the substrate; and a bonded layer (), including the lighting component (), the lighting component () being connected to the integrated circuit layer () through flip-chip bonding or monolithic integration.

Power system-on-chip architecture

The subject disclosure presents power semiconductor devices, and methods for manufacture thereof, with a low on-state voltage drop and a low turn-off energy. In an aspect, a power semiconductor device is provided that embodies a normally off trench gate-controlled p-i-n switch with a charge trapping material in the gate dielectric and a self-depleted channel.

Gate-controlled p-i-n switch with a charge trapping material in the gate dielectric and a self-depleted channel

Providing for a monolithic magnetic induction device having low DC resistance and small surface area is described herein. By way of example, the magnetic induction device can comprise a substrate (e.g., a semiconductor substrate) having trenches formed in a bottom layer of the substrate, and holes formed in the substrate between the trenches and an upper layer of the substrate. Additionally, the magnetic induction device can comprise a conductive coil embedded or deposited within the trenches. The magnetic induction device can further comprise a set of conductive vias formed in the holes that electrically connect the bottom layer of the substrate with the upper layer. Further, one or more integrated circuit components, such as active devices, can be formed in the upper layer, at least in part above the conductive coil. The vias can be utilized to connect to integrated circuit components with the conductive coil, where suitable.

Monolithic magnetic induction device

The subject disclosure presents power semiconductor devices, and methods for manufacture thereof, with improved ruggedness and. In an aspect, the power semiconductor devices are power field effect transistors (FETs) having enhanced suppression of the activation of the parasitic bipolar junction transistor (BJT) and a normal threshold value. The devices comprise a doped source () of a first conductivity type, a doped body () of a second conductivity type, a source electrode () short-connecting the doped body and the doped source, a doped drift region () of the first conductivity type, a first layer () of a gate dielectric region () covering the surface of the doped drift region (), and forming channel from the doped source () to the doped drift region (), a second layer () of the gate dielectric region () over the first layer (), a third layer () of the gate dielectric region () over the second layer (), and a gate electrode () over the third layer ().

Power semiconductor field effect transistor structure with charge trapping material in the gate dielectric

Methods and apparatus described herein are associated with integrated magnetic induction devices. A magnetic induction device can include a groove formed in a substrate, a magnetic core included in the groove and surrounded by a conductive winding that is adjacent to portion(s) of the substrate, and respective insulation layers included between the substrate and the conductive winding and between the magnetic core and the conductive winding. An inductor can further include conductive vias formed in the substrate and connected to respective portions of the conductive winding. Further, a transformer can include a groove formed in a substrate, a closed-loop/gapped magnetic core included in the groove and surrounded by first and second conductive windings that are adjacent to respective portions of the substrate, and respective insulation layers formed between the substrate and the first and second conductive windings, and between the closed-loop/gapped magnetic core and the first and second conductive windings.

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Hong Kong, China

Johnny Kin On Sin