Texas Instruments Corporation

Burr-brown Corporation

Johnnie F Molina

Hugo Cheung

Rodney T Burt

Robert M Stitt, Ii

R Mark Stitt, Ii

Keith Eric Sanborn

Ramesh Saripalli

Rituparna Ghosh

A power-on reset (POR) circuit includes a first transistor (MP) having a source coupled to a first supply voltage (V) and a gate coupled to a second supply voltage (GND). A resistor (R) has a first terminal coupled by a depletion mode transistor (JP) to the second supply voltage and a second terminal coupled to a drain of the first transistor. A Schmitt trigger () has an input coupled to receive a first signal (V) on a conductor () coupled to the second terminal of the resistor and a terminal of a capacitor (C), for producing an output voltage (V) representative of a power-on reset signal (V) in response to an interruption of the first supply voltage (V).

Low current power-on reset circuit and method

In a data acquisition system, digitizing circuitry (A) is powered up by a control signal (ADC_CONVST), superimposing a glitch (-) on a first multiplexed and amplified signal value (V) received by the digitizing circuitry. Sampling and holding of the first multiplexed and amplified signal value occurs during a delay provided between the glitch and a beginning of a first A/D conversion of the first multiplexed and amplified signal value to allow settling of the glitch. After the first conversion begins, a second multiplexed and amplified signal value is generated. The digitizing circuitry performs the first A/D conversion during initial settling of the second multiplexed and amplified signal value and then is powered down while the second multiplexed and amplified signal value continues to settle.

Low power, high speed multi-channel data acquisition system and method

A signal generating circuit includes a relaxation oscillator operating to alternately generate a first ramp signal that is periodic at a frequency of the relaxation oscillator and a second ramp signal that is periodic at the frequency of the relaxation oscillator and is out of phase with respect to the first ramp signal The first ramp signal is compared to a first reference voltage and the state of a first flip-flop is changed if the first ramp signal exceeds the first reference voltage. The second ramp signal is compared to the first reference voltage and the state of a second flip-flop is changed if the second ramp signal exceeds the first reference voltage. The first flip-flop is reset in response to a first level of the first ramp signal and the second flip-flop is reset in response to a second level of the second ramp signal. A logical ORing function is performed on an output of the first flip-flop and an output of the second flip-flop to produce an output signal having a frequency that is a multiple of the relaxation oscillator frequency.

Analog circuit and method for multiplying clock frequency

A method and circuit for frequency synthesis using a low drift current controlled oscillator configured to provide a wide output frequency and high accuracy are provided. An exemplary frequency synthesis circuit is configured for programmable control of a center frequency of the current controlled oscillator to provide a wide range of output frequencies with high accuracy. In accordance with an exemplary embodiment of the present invention, an exemplary circuit comprises a phase-locked loop (PLL) circuit comprising a phase detector, a charge pump, a current controlled oscillator and a divider circuit. For programmable control of the current controlled oscillator, the PLL circuit further comprises a trim digital-to-analog converter (DAC) configured to provide a trimmed current signal for control of the current controlled oscillator. In accordance with an exemplary embodiment of the present invention, trim values for operation of the trim DAC can be suitably located within a trim register of flash memory, such as programmable flash memory within any mixed-signal device or system.

Method and circuit for frequency synthesis using a low drift current controlled oscillator with wide output frequency range

A circuit for reducing input offset error and improving gain switching speed in a programmable gain amplifier includes a level shifting buffer that senses a signal on a common mode conductor in a differential input stage of an operational amplifier, and shifts the level of that signal up to the level corresponding to a level of an input signal applied to a non-inverting input of the operational amplifier. If a gain select signal is at a first logic level, the voltage produced by the buffer is applied to a gate electrode of one of a plurality of gain switching JFETs coupling a gain network to the inverting input of the operational amplifier, turning that JFET on. If the gain select signal is at a second logic level, the output of the buffer is isolated from the gain switching JFET and a turn off voltage is applied to the gate of the gain switching JFET.

Programmable gain amplifier circuitry and method for biasing JFET gain

A technique for reducing phase shift of a signal passing through a large thin film resistor on an insulating layer includes applying a signal to one terminal of the thin film resistor and also to one end of an underlying doped epitaxial region. The opposite terminal of the thin film resistor is connected to a virtual ground or virtual reference voltage produced by an inverting input of an operational amplifier. The corresponding opposite end of the epitaxial layer is connected to ground or other reference voltage. The voltage gradients produced by currents flowing through both the thin film resistor and the epitaxial layer are equal, so that substantially no incremental charging current flows through capacitance between the thin film resistor and the epitaxial layer. Phase shift of the signal flowing through the thin film resistor is thereby avoided.

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Tucson, AZ, United States of America

Johnnie F Molina