Infineon Technologies Ag

Johnathan Edmonds

Torsten Partsch

Jennifer Faye Huckaby

Tao Tian

Matt Welch

Leonel R Nino

A method of self-repair for a DRAM integrated circuit includes internally generating a bit pattern and writing the pattern to an array of memory cells within the integrated circuit. The DRAM integrated circuit reads from the array and internally compares the read data with the generated pattern to determine addresses for failed memory cells. The DRAM integrated circuit sets internal soft fuses that record the addresses of the failed memory cells and provide substitute memory cells for the failed memory cells from a redundant memory portion of the array. The self-repair process occurs each time the DRAM integrated circuit is powered up, thus permitting the integrated circuit to adapt to failures when installed in electronic devices and lessening the need for repair during manufacturing.

Method of self-repairing dynamic random access memory

The present invention relates to a memory system including an external clock and a memory chip connected to the external clock. The external clock generates an operating signal at an operating frequency that controls at least one electrical component of the memory system. The memory chip includes a frequency detector that detects at least a range of frequency values for the operating frequency. Further, the frequency detector includes a reference frequency generator that generates a reference signal at a reference frequency.

On-die detection of the system operation frequency in a DRAM to adjust DRAM operations

The present invention relates to a method of operating a memory system comprising a memory chip. An operating signal is generated at an operating frequency. The operating frequency is applied to the memory chip to control one or more electrical components of the memory system. A reference signal is generated at a reference frequency within the memory chip and a range of values for the operating frequency is detected based on the reference signal and the operating signal.

Method for on-die detection of the system operation frequency in a DRAM to adjust DRAM operations

A method of protecting an integrated circuit that includes sensing a temperature of an integrated circuit, comparing the sensed temperature with a threshold temperature and controlling operation of the integrated circuit based on the comparing.

Use of an on-die temperature sensing scheme for thermal protection of DRAMS

A method of throttling the frequency with which an integrated circuit is accessed includes sensing the temperature of the integrated circuit die and converting the sensed temperature to a digital signal. The digital signal is stored in a register of the integrated circuit. The digital signal is read, and the frequency with which the integrated circuit is accessed is adjusted dependent at least in part upon the temperature of the die as indicated by the digital signal.

Method and apparatus for temperature throttling the access frequency of an integrated circuit

A method of protecting an integrated circuit that includes sensing a temperature of an integrated circuit that has a data pin, generating a temperature data signal based on the sensing, implementing a temperature sensing protocol and supplying the temperature data signal to the data pin based on the temperature sensing protocol.

Use of DQ pins on a ram memory chip for a temperature sensing protocol

A method of using a memory chip includes operating a memory chip of a memory system and sending a command signal to the memory chip, wherein the command signal contains information regarding an operational frequency of a system clock signal of the memory system. The method provides the advantage of enabling high operation frequencies and thus increasing the SDRAM internal timing margin.

Indication of the system operation frequency to a DRAM during power-up

A tunable analog-to-digital converter which generates samples having M-bits for use with an operating circuit. The operating circuit generates a first enable signal to instruct the analog-to-digital converter to turn on. Additionally, a sensor generates an analog signal in response to a condition. The tunable analog-to-digital converter includes a primary analog-to-digital converter which receives the analog signal and converts the analog signal to a primary digital signal upon receipt of the first enable signal. The tunable analog-to-digital converter also includes a comparator and a secondary analog-to-digital converter. The comparator compares the value of the primary digital signal to a predetermined value and generates a second enable signal depending on the value of the primary digital signal and the predetermined value. The secondary analog-to-digital converter receives the analog signal and converts the analog signal to a secondary digital signal upon receipt of the second enable signal.

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Cary, NC, United States of America

Johnathan Edmonds