Maspar Computer Corporation

Marpar Computer Corporation

Maspar Computer Company

John Zapisek

John R Nickolls

Won Sub Kim

William T Blank

W Thomas Blank

Kevin Van Horn

Jeffrey C Kalb

David M Bulfer

Jeffery C Kalb

John M Long

Mark P McKee

A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.

Scalable processor to processor and processor to I/O interconnection

To effect a block data transfer between a plurality of physical I/O devices coupled through interfaces to an I/O channel ('IOC') bus, a source logical device is established by programmably assigning to each of the physical device interfaces a logical device identifier, a leaf identifier determining when the physical device participates relative to the first data transfer in the block data transfer, a burst count specifying the number of consecutive transfers for which the physical device is responsible when its interleave period arrives, and an interleave factor identifying how often the physical device participates in the block data transfer. A destination logical device is similarly established. The source and logical devices are then activated to accomplish a block transfer of data between them. To permit different I/O processors to operate independently in making I/O requests, requests from each I/O processor are communicated to an IOC controller over another bus, which need not be a high performance bus, and are serviced to construct header packets in a transaction buffer identifying IOC transactions, including source and destination logical devices. When each packet is finished, the responsible I/O processor puts a pointer into a transaction queue, which is a FIFO register. Each IOC transaction is initiated as its corresponding pointer is popped from the transaction queue. Apparatus embodiments are disclosed as well.

Broadcasting headers to configure physical devices interfacing a data

A router circuit for selectively connecting an input terminal of the router circuit to either a specified output terminal of the router circuit (crossbar personality) or to any of a group of output terminals of the router circuit associated with a single output channel (hyperbar personality). The router circuit is made configurable as either a crossbar switch or a hyperbar switch by dividing the router chip into sections, where each section is associated with a group of input terminals, and wherein various grant circuits within each of the sections have enable/disable input terminals connected by controllable switches to either enable/disable output terminals of grant circuits in an adjacent section (hyperbar personality) or to fixed logic levels (crossbar personality). In the crossbar configuration, for each input terminal of a section, only one grant circuit per channel is enabled. Each of the sections has a different set of grant circuits enabled per channel so that no two sections can access a same output terminal of the router chip. In the hyperbar configuration, the sections are made transparent, and grant circuits are enabled or disabled depending on output wire availability. Additionally, the router circuit contains novel routing address bit and protocol bit circuitry as well as novel diagnostic circuitry for detecting broken wires between router circuits.

Diagnostic circuitry

A router circuit for selectively connecting an input terminal of the router circuit to either a specified output terminal of the router circuit (crossbar personality) or to any of a group of output terminals of the router circuit associated with a single output channel (hyperbar personality). The router circuit is made configurable as either a crossbar switch or a hyperbar switch by dividing the router chip into sections, where each section is associated with a group of input terminals, and wherein various grant circuits within each of the sections have enable/disable input terminals connected by controllable switches to either enable/disable output terminals of grant circuits in an adjacent section (hyperbar personality) or to fixed logic levels (crossbar personality). In the crossbar configuration, for each input terminal of a section, only one grant circuit per channel is enabled. Each of the sections has a different set of grant circuits enabled per channel so that no two sections can access a same output terminal of the router chip. In the hyperbar configuration, the sections are made transparent, and grant circuits are enabled or disabled depending on output wire availability. Additionally, the router circuit contains novel routing address bit and protocol bit circuitry as well as novel diagnostic circuitry/or detecting broken wires between router circuits.

Router chip for processing routing address bits and protocol bits using

Router chip with quad-crossbar and hyperbar personalities

Scalable processor to processor and processor-to-I/O interconnection

A massively parallel processor includes an array of processor elements (20), of PEs, and a multi-stage router interconnection network (30), which is used both for I/O communications and for PE to PE communications. The I/O system (10) for the massively parallel processor is based on a globally shared addressable I/O RAM buffer memory (50) that has address and data buses (52) to the I/O devices (80, 82) and other address and data buses (42) which are coupled to a router I/O element array (40). The router I/O element array is in turn coupled to the router ports (e.g. S2.sub.-- 0.sub.-- X0) of the second stage (430) of the router interconnection network. The router I/O array provides the corner turn conversion between the massive array of router lines (32) and the relatively few buses (52) to the I/O devices.

Input/output system for parallel processing arrays

Growing community of inventors

Cupertino, CA, United States of America

John Zapisek