International Business Machines Corporation

Globalfoundries Inc.

John Z Colt, Jr

Nancy T Pascoe

Raymond James Bunkofske

Maheswaran Surendra

Marc A Taubenblatt

Asif Ghias

James J McGill

John J Ellis-Monaghan

Steven M Shank

Leah M Pastel

Venkata Nagaraju Pavuluri

Perry G Hartswick

Brian Christopher Barker

John W Lewis

A computer-implemented method, system, and/or computer program product controls manufacturing devices in a manufacturing environment. One or more processors receive sensor readings, which detect conditions that are unique to different areas within the manufacturing environment, in order to generate models of operations for each area in the manufacturing environment. One or more processors generate an ensemble model by extracting information from the models to describe a relationship between the conditions. One or more processors generate a device control signal, based on the ensemble model, that adjusts operations in the different areas in order to ameliorate the detected conditions.

Use of multivariate models to control manufacturing operations

Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.

Lateral silicon-on-insulator bipolar junction transistor process and structure

A semiconductor wafer including a plurality of pits in the semiconductor wafer. The pits are arranged in an information-providing pattern and are readable after completion of processing on the wafer.

Wafer identification mark

A method and structure for controlling a manufacturing tool includes measuring different manufacturing parameters of the tool, transforming a plurality of time series of the manufacturing parameters into intermediate variables based on restrictions and historical reference statistics, generating a surrogate variable based on the intermediate variables, if the surrogate variable exceeds a predetermined limit, identifying a first intermediate variable, of the intermediate variables, that caused the surrogate variable to exceed the predetermined limit and identifying a first manufacturing parameter associated with the first intermediate variable, and inhibiting further operation of the tool until the first manufacturing parameter has been modified to bring the surrogate value within the predetermined limit.

User configurable multivariate time series reduction tool control method

An integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such as resistors, or active devices such as diodes, bipolar transistors or field effect transistors (FETs). A multi-layer semiconductor body is formed of, preferably silicon and silicon dioxide. A conducting region or channel is formed in one or more of the layers. For the FET, silicon above and below the channel region provides controllable gates with vertically symmetrical device characteristics. Buried insulator layers may be added to isolate the lower gate of individual devices from each other and to create multiple vertically stacked isolated devices. Both PFET and NFET devices can be made with independent doping profiles in both depletion and accumulation modes.

Double silicon-on-insulator device and method thereof

Double silicon-on-insulator device and method therefor

Growing community of inventors

Williston, VT, United States of America

John Z Colt, Jr