International Business Machines Corporation

John Youssef Sayah

Liang-Jie Zhang

Tian-Jy Chao

Hung-Yang Chang

Jen-Yao Chung

Yiming Ye

Yu Long

Haiyan Wang, Legal Representative

Jing Min Xu

Santhosh Babu Kumaran

Shun Xiang Yang

Philip S Honsinger

Vinod Narayanan

Ying Nan Zuo

Qun Zhou

Rajesh Gupta

Hung-yang (Henry) Chang

Robert A Rozwod

An adaptive integration activity management framework for on demand business process integration provides a mechanism to enable easy integration of legacy and new applications. The framework minimizes the effort need to integrate a new application into an existing business process environment such that the new activity is a 'plug-in' into an action manager by implementing a standard adaptation layer. Activity integration is implemented in the principle of 'on-demand' because it is invoked as required, so the communication and collaboration between partners become much more flexible.

Method and apparatus of adaptive integration activity management for business application integration

Hyperchain information management techniques are provided for use in applications such as on-demand business collaboration. In accordance with such techniques, a hyperchain annotation methodology is provided. Such an annotation methodology enables interaction between loosely-coupled business processes or interacting partners and business entities. Annotated information components and process components for collaboration may be expressed as links. Further, techniques for realizing an on-demand message exchange, embedded status/state information, flexible collaborative business message exchange patterns, and a collaborative directory are provided.

Methods and apparatus for information hyperchain management for on-demand business collaboration

Techniques are provided for product life cycle management over an information network. More particularly, techniques are provided for decision support activation and management in accordance with a product life cycle management process such as a collaborative design process. In one aspect of the invention, a technique for managing at least one collaborative process performed in accordance with a first entity and at least a second entity, comprises the following steps/operations. Information associated with the at least one collaborative process is obtained. Based on at least a portion of the obtained information, an information structure (e.g., a context pyramid) representative of the collaborative process is dynamically maintained so as to assist at least one of the first entity and the second entity in managing at least a portion of the collaborative process.

Decision support activation and management in product life cycles using a context pyramid structure

A system and method for capturing a plurality of business requirements using a Business Process Outsourcing Language (BPOL), an XML representation for expressing business process flow rules, preferences, business rules and event-action mappings as well as service links, to automate the process of generating business processes for use with Web services. BPOL is used to dynamically construct a search script for an advanced Web services discovery engine to find Web services from both UDDI registries and Web services Inspection Language (WSIL) documents and then create a qualified service list. Then a service selection problem is mapped into a solution space {0,1} for use by an optimization algorithm that performs second level service selection of the best set of services based on the requirements.

System and method of dynamic service composition for business process outsourcing

A method and apparatus for detecting valid placement of library cells on chip images or hierarchy design images may be accomplished by determining a periodic pattern of the chip image, or hierarchical image. Once the repetitive pattern is recognized, this pattern is represented by a binary vector. Similarly, a binary vector is created for a particular cell library that is to be placed on the chip image or hierarchical design image. When the placement algorithm places the library cell on the chip or hierarchical image, the binary vector of the library cell is folded over a folded binary vector of the chip image or hierarchical design image to produce a component delta set. In essence, the component delta set indicates spacing violations between the library cell and the chip or hierarchical design image. When such a spacing violation is recognized, the placement algorithm can immediately reposition the library cell.

Method and apparatus for placing and detecting prewire blockages of

A computer model for facilitating computer assisted design includes data structures which are flexibly organized by storing of information in accordance with entities or simulations thereof (including symbolic layer entities, area entities, area spec entities and area spec usage pattern entities), which are hierarchically associated both by relationships between them at a given level of abstraction of the physical entity they represent and by various attributes that correspond to different levels of abstraction in graphs. The graphs are freely mappable onto any desired fixed data structure such as a hierarchical area tree. Each hierarchical level and particularly the symbolic layer entity within the computer model provides data hiding at each lower level thereof and thus provides data hiding in the fixed data structure by virtue of the mapping function in order to reduce data processing overhead for manipulation of the fixed data structure. Further spatial restriction within one or more symbolic layers is provided by means of an applications window entity. Data compaction is provided by provision of data sharing of area spec entities by plural area entities which are otherwise uniquely maintained.

Hierarchical data model for design automation

A method for resizing the macro cells' boundaries of an integrated chip is disclosed and that becomes effectual after the initial floorplanning process has been completed. The method of the present invention apportions any excess area that is freed-up after the initial floorplanning process by altering the sizes or dimensions of the macro cell within the hierarchy of the integrated circuit in such a manner that the fractional change in the percentage occupancy is substantially constant among all macro cells at all hierarchy levels.

Chip sizing for hierarchical designs

A method for restructuring information stored in physical design image form, such as an image of a layer in a semiconductor package, into a hierarchical area specification model useful in automated design applications. The restructuring results in recognizing identical patterns in the image and storing common information about the patterns in a single location to decrease storage space required and improve access efficiency by design application programs needing the information. Parameters controlling the method can be adjusted to produce a hierarchical model that is particularly suited to the needs of a particular application program.

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John Youssef Sayah