Texas Instruments Corporation

Other

John Y Fong

Sudhir Kumar Madan

Hugh Pryor McAdams

Sung-Wei Lin

James W Grace

Juergen T Rickes

Ralph H Lanham

Anand Seshadri

Jarrod Eliason

The present invention facilitates memory devices and operation thereof by employing a repair cache systemto correct or repair identified faulty memory locations. The repair cache systemincludes a decoder that selects local repair location addresses from repair setsaccording to a repair region address. Comparatorscompare the selected local repair location addresses with a local repair addressto identify a match. Repair register banksthat comprise a plurality of repair registers are selected if an associated comparatoridentifies a match. Then, a register within the associated register bank is selected according the repair region addressfor read/write access. If a match is not identified, a memory location from a main memoryis selected for read/write access.

Decoder based set associative repair cache systems and methods

An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

Low resistance plate line bus architecture

A memory circuit and method to reduce wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (, and) and columns (). A first conductor () is coupled to a plurality of the rows (, and) of memory cells. A first transistor () has a current path coupled between a voltage supply terminal () and the first conductor () and a control terminal coupled to receive a first control signal (PLV). A second transistor () has a current path coupled between the voltage supply terminal and the first conductor and a control terminal coupled to receive a second control signal (PLW).

Plateline driver with RAMP rate control

Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.

Accelerated low power fatigue testing of FRAM

Methods () and ferroelectric devices () are presented, in which pulses () are selectively applied to platelines (PL) of one or more non-selected ferroelectric memory cells () during memory access operations to mitigate cell storage node disturbances.

Plateline voltage pulsing to reduce storage node disturbance in ferroelectric memory

A memory circuit and method for reducing gate oxide stress is disclosed. The circuit includes a memory cell for storing data. The memory cell has a first and a second control terminal and a pass transistor . The pass transistor has a control gate coupled to the first control terminal. The memory circuit includes a drive circuit having an output terminal coupled to the second control terminal. The drive circuit is arranged to produce a control signal PL having a rise time and a fall time, wherein the fall time is greater than the rise time.

Circuit and method for reducing access transistor gate oxide stress

A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be rapidly repeated. In one embodiment, the FeRAM includes multiple segments with plate lines in each segment being isolated from plate lines in other segments. A first fatigue operation uses standard read/write decoding for word lines but simultaneously activates all segments. A second fatigue operation activates all segments and all plate lines and exercises one row of memory cells in each plate line group. A third fatigue operation is similar to the second but cycles through rows in the plate line groups so that a number of repetitions of the third fatigue operation equally fatigue every FeRAM cell.

Accelerated fatigue testing

A method and circuit for measuring a charge distribution for readout from FeRAM cells is fast enough for an on-chip defect detection and parameter adjustment. A comparator-type sense amplifier and a reference voltage generator measure a bit line charge or voltage using one readout of charge from an FeRAM cell and comparisons of the resulting bit line voltage to a series of reference voltages. A series of result signals from the sense amplifier indicates when the bit line voltage is approximately equal to the reference voltage. The results signals can be output for analysis and/or used internally for defect detection or setting of operating parameters such as a reference used during read operations.

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Allen, TX, United States of America

John Y Fong